Unfaithful Glitch Propagation in Existing Binary Circuit Models

We show that no existing continuous-time, binary value-domain model for digital circuits is able to correctly capture glitch propagation. Prominent examples of such models are based on pure delay channels (P), inertial delay channels (I), or the elaborate PID channels proposed by Bellido-D\'iaz et al. We accomplish our goal by considering the solvability/non-solvability border of a simple problem called Short-Pulse Filtration (SPF), which is closely related to arbitration and synchronization. On one hand, we prove that SPF is solvable in bounded time in any such model that provides channels with non-constant delay, like I and PID. This is in opposition to the impossibility of solving bounded SPF in real (physical) circuit models. On the other hand, for binary circuit models with constant-delay channels, we prove that SPF cannot be solved even in unbounded time; again in opposition to physical circuit models. Consequently, indeed none of the binary value-domain models proposed so far (and that we are aware of) faithfully captures glitch propagation of real circuits. We finally show that these modeling mismatches do not hold for the weaker eventual SPF problem.Comment: 23 pages, 15 figure

A Digital Delay Model Supporting Large Adversarial Delay Variations

Dynamic digital timing analysis is a promising alternative to analog simulations for verifying particularly timing-critical parts of a circuit. A necessary prerequisite is a digital delay model, which allows to accurately predict the input-to-output delay of a given transition in the input signal(s) of a gate. Since all existing digital delay models for dynamic digital timing analysis are deterministic, however, they cannot cover delay fluctuations caused by PVT variations, aging and analog signal noise. The only exception known to us is the $\eta$-IDM introduced by F\"ugger et al. at DATE'18, which allows to add (very) small adversarially chosen delay variations to the deterministic involution delay model, without endangering its faithfulness. In this paper, we show that it is possible to extend the range of allowed delay variations so significantly that realistic PVT variations and aging are covered by the resulting extended $\eta$-IDM

Experimental Validation of a Faithful Binary Circuit Model

International audienceFast digital timing simulations based on continuous-time, digital-value circuit models are an attractive and heavily used alternative to analog simulations. Models based on analytic delay formulas are particularly interesting here, as they also facilitate formal verification and delay bound synthesis of complex circuits. Recently, Függer et al. (arXiv:1406.2544 [cs.OH]) proposed a circuit model based on so-called involution channels. It is the first binary circuit model that realistically captures solvability of short-pulse filtration, a non-trivial glitch propagation problem related to building one-shot inertial delays. In this work, we address the question of whether involu-tion channels also accurately model the delay of real circuits. Using both Spice simulations and physical measurements, we confirm that modeling an inverter chain by involution channels accurately describes reality. We also demonstrate that transitions in vanishing pulse trains are accurately predicted by the involution model. For our Spice simulations, we used both UMC-90 and UMC-65 technology, with varying supply voltages from nominal down to near sub-threshold range. The measurements were performed on a special-purpose UMC-90 ASIC that combines an inverter chain with low-intrusive high-speed on-chip analog amplifiers

An Accurate Hybrid Delay Model for Multi-Input Gates

Accurately modeling the delay of multi-input gates is challenging due to variations caused by switching different inputs in close temporal proximity. This paper introduces a hybrid model for a CMOS NOR gate, which is based on replacing transistors with time-variant resistors. We analytically solve the resulting non-constant coefficient differential equations and derive expressions for the gate delays, which also paved the way to an empirical parametrization procedure. By comparison with Spice simulation data, we show that our model indeed faithfully represents all relevant multi-input switching effects. Using an implementation in the Involution Tool, we also demonstrate that it surpasses the few alternative models known so far in terms of accuracy

Model-checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

International audienceAsynchronous circuits have key advantages in terms of low energy consumption, robustness, and security. However , the absence of a global clock makes the design prone to deadlock, livelock, synchronization, and resource-sharing errors. Formal verification is thus essential for designing such circuits, but it is not widespread enough, as many hardware designers are not familiar with it and few verification tools can cope with asyn-chrony on complex designs. This paper suggests how an industrial design flow for asynchronous circuits, based upon the standard HDL SystemVerilog, can be supplemented with formal verification capabilities rooted in concurrency theory and model-checking technology. We demonstrate the practicality of our approach on an industrial asynchronous circuit (4000 lines of SystemVerilog) implementing a memory protection unit

Imperfections

This open access book synthesizes the swiftly growing critical scholarship on mistakes, glitches, and other aesthetics and logics of imperfection into the first transdisciplinary, transnational framework of imperfection studies. In recent years, the trend to present the notion of imperfection as a plus rather than a problem has resonated across a range of social and creative disciplines and a wealth of world localities. As digital tools allow media users to share ever more suave selfies and success stories, psychologists promote 'the gifts of imperfections' and point to perfectionism as a catalyst for rising depression and burnout complaints and suicide rates among millennials. As sound technologies increasingly permit musicians to 'smoothen' their work, composers increasingly praise glitches, noise, and cracks. As genetic engineering upgrades with swift speed, philosophers, marketeers, and physicians plea 'against perfection' and supermarkets successfully advertise 'perfectly imperfect' vegetables. Meanwhile, cultural analysts point at skewed perspectives, blurry images, and other 'deliberate imperfections' in new and historical cinema, painting, photography, music, and literature. While these and other experts applaud imperfection, scholars in fields ranging from disability studies to tourism critically interrogate a trend to fetishize imperfection and poverty. They rightfully warn against projecting privileged (and, often, emphatically western-biased) feel-good stories onto the less privileged, the distorted, and the frail. The editors unite the different strands in imperfection thinking across various disciplines tools. In fourteen chapters by experts from different world localities, they offer scholars and students more historically grounded and more critically informed conceptualizations of the imperfect. This book is available as open access through the Bloomsbury Open programme and is available on www.bloomsburycollections.com

Imperfections:Studies in Mistakes, Flaws, and Failures

In recent years, the trend to present the notion of imperfection in a positive rather than negative light has resonated across a range of social and creative disciplines and a wealth of world regions. This open access book synthesizes the swiftly growing critical scholarship on mistakes, glitches, and other aesthetics and logics of imperfection into the first transdisciplinary, transnational framework of imperfection studies. With this framework, the editors offer scholars and students across various disciplines tools to craft more historically grounded and critically informed conceptualizations of the imperfect