Design for manufactureability with regular fabrics in digital integrated circuits

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 113-115).Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the designs that generate the least systematic process variation, e.g., from pattern dependent effects, but must also build circuits that are robust to the remaining process or environmental random variations. This research addresses both ideas, by examining integrated circuit design styles and aspects that can help curb process variation and improve manufacturability and performance in future technology generations. One suggested method to reduce variation sensitivity in system designs has been the concept of design regularity. Long used in FPGAs, and SRAMs, the concept of repeatable blocks is examined in this work as a method of reducing circuit variation. Layout based variation is examined in three designs with different distinctions of regularity: a Via-Patterned Gate Array (VPGA) FPU, a Berkeley BEE-generated decoder, and a low power FPGA. The circuit level impact on variation is also considered, by examining several circuit architectures. This includes analysis of the novel Limited Switch Dynamic Logic (LSDL) style, which reduces design area and encourages regularity through minimum logic sizing.(cont.) Robustness to spatial variation and slanted plane effects is examined with a common-centroid based layout methodology for digital integrated circuits. Finally, a methodology is introduced in the form of the Monte Carlo Variation Analysis Engine whereby distributed process variables are fed into repeated simulation runs, output metrics are recorded, and regressions are measured to expose design sensitivities. The results for different layout and circuit design styles identify improvements that may be made to improve robustness to variation. We show that design regularity is a significant factor in mitigating sensitivity to process variation and is worthy of further examination.by Mehdi Gazor.S.M

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots