2,270 research outputs found

    Design methodology and productivity improvement in high speed VLSI circuits

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    2017 Spring.Includes bibliographical references.To view the abstract, please see the full text of the document

    The MANGO clockless network-on-chip: Concepts and implementation

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    Ready To Roll: Southeastern Pennsylvania's Regional Electric Vehicle Action Plan

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    On-road internal combustion engine (ICE) vehicles are responsible for nearly one-third of energy use and one-quarter of greenhouse gas (GHG) emissions in southeastern Pennsylvania.1 Electric vehicles (EVs), including plug-in hybrid electric vehicles (PHEVs) and all-electric vehicles (AEVs), present an opportunity to serve a significant portion of the region's mobility needs while simultaneously reducing energy use, petroleum dependence, fueling costs, and GHG emissions. As a national leader in EV readiness, the region can serve as an example for other efforts around the country."Ready to Roll! Southeastern Pennsylvania's Regional EV Action Plan (Ready to Roll!)" is a comprehensive, regionally coordinated approach to introducing EVs and electric vehicle supply equipment (EVSE) into the five counties of southeastern Pennsylvania (Bucks, Chester, Delaware, Montgomery, and Philadelphia). This plan is the product of a partnership between the Delaware Valley Regional Planning Commission (DVRPC), the City of Philadelphia, PECO Energy Company (PECO; the region's electricity provider), and Greater Philadelphia Clean Cities (GPCC). Additionally, ICF International provided assistance to DVRPC with the preparation of this plan. The plan incorporates feedback from key regional stakeholders, national best practices, and research to assess the southeastern Pennsylvania EV market, identify current market barriers, and develop strategies to facilitate vehicle and infrastructure deployment

    Analysis domain model for shared virtual environments

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    The field of shared virtual environments, which also encompasses online games and social 3D environments, has a system landscape consisting of multiple solutions that share great functional overlap. However, there is little system interoperability between the different solutions. A shared virtual environment has an associated problem domain that is highly complex raising difficult challenges to the development process, starting with the architectural design of the underlying system. This paper has two main contributions. The first contribution is a broad domain analysis of shared virtual environments, which enables developers to have a better understanding of the whole rather than the part(s). The second contribution is a reference domain model for discussing and describing solutions - the Analysis Domain Model

    Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

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    The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

    Automation, Protection and Control of Substation Based on IEC 61850

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    Reliability of power system protection system has been a key issue in the substation operation due to the use of multi-vendor equipment of proprietary features, environmental issues, and complex fault diagnosis. Failure to address these issues could have a significant effect on the performance of the entire electricity grid. With the introduction of IEC 61850 standard, substation automation system (SAS) has significantly altered the scenario in utilities and industries as indicated in this thesis

    Hierarchical Agent-based Adaptation for Self-Aware Embedded Computing Systems

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    Siirretty Doriast

    The Critical Role of Public Charging Infrastructure

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    Editors: Peter Fox-Penner, PhD, Z. Justin Ren, PhD, David O. JermainA decade after the launch of the contemporary global electric vehicle (EV) market, most cities face a major challenge preparing for rising EV demand. Some cities, and the leaders who shape them, are meeting and even leading demand for EV infrastructure. This book aggregates deep, groundbreaking research in the areas of urban EV deployment for city managers, private developers, urban planners, and utilities who want to understand and lead change
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