Uncertainty of measurement with ADC for slowly proceed processes

Развитие цифровой техники с одной стороны и внедрение европейских стандартов по испытаниям с другой стороны обуславливают необходимость оценки неопределенности измерительных каналов информационно-измерительных систем. В статье рассмотрены основные типы аналогово-цифровых преобразователей и составляющие неопределенности, возникающие при преобразовании измерительных сигналов из аналогового вида в цифровой код. На примере микроконтроллера ATmega164 определены виды погрешностей, которые вносят существенный вклад в бюджет неопределенности при преобразованиях измерительных сигналов поступающих от первичных преобразователей контролирующих медленно протекающие процессы. Основываясь на составляющих неопределенности описанных в технической документации на микроконтроллер, составлен бюджет неопределенности аналого-цифрового преобразования. Приведен порядок расчета суммарной, стандартной и расширенной неопределенности АЦП с учетом коэффициента охвата.The development of digital technology on the one hand and the introduction of European standards of tests on the other hand necessitate estimating uncertainty of measuring channels of information-measuring systems. The article describes the main types of analog-to-digital converters. The definition quantitate error, differential nonlinearity, offset voltage, the multiplicative error monotony conversion characteristics, aperture errors occur when converting the measurement signals from an analog signal to a digital code. A brief description of the metrological characteristics of the ATmega164 microcontroller and his example defines the types of errors that contribute significantly to the uncertainty budget under the transformations of the measurement signals coming from primary converters controlling slow flowing processes. The analysis of technical documentation ATmega164 microcontroller and components defined transformations uncertainty. According to the PM X 33.1405-2005 recommendations for evaluation of uncertainty in carrying out metrological works composed uncertainty budget. The formulas for calculating the standard uncertainty assessment. The order of calculation of the total uncertainty and the extended analog-to-digital conversion, taking into account the coverage ratio

A Fast Digital Integrator for magnetic measurements

In this work, the Fast Digital Integrator (FDI), conceived for characterizing dynamic features of superconducting magnets and measuring fast transients of magnetic fields at the European Organization for Nuclear Research (CERN) and other high-energy physics research centres, is presented. FDI development was carried out inside a framework of cooperation between the group of Magnet Tests and Measurements of CERN and the Department of Engineering of the University of Sannio. Drawbacks related to measurement time decrease of main high-performance analog-to-digital architectures, such as Sigma-Delta and integrators, are overcome by founding the design on (i) a new generation of successive-approximation converters, for high resolution (18-bit) at high rate (500 kS/s), (ii) a digital signal processor, for on-line down-sampling by integrating the input signal, (iii) a custom time base, based on a Universal Time Counter, for reducing time-domain uncertainty, and (iv) a PXI board, for high bus transfer rate, as well as noise and heat immunity. A metrological analysis, aimed at verifying the effect of main uncertainty sources, systematic errors, and design parameters on the instrument performance is presented. In particular, results of an analytical study, a preliminary numerical analysis, and a comprehensive multi-factor analysis carried out to confirm the instrument design, are reported. Then, the selection of physical components and the FDI implementation on a PXI board according to the above described conceptual architecture are highlighted. The on-line integration algorithm, developed on the DSP in order to achieve a real-time Nyquist bandwidth of 125 kHz on the flux, is described. C++ classes for remote control of FDI, developed as a part of a new software framework, the Flexible Framework for Magnetic Measurements, conceived for managing a wide spectrum of magnetic measurements techniques, are described. Experimental results of metrological and throughput characterization of FDI are reported. In particular, in metrological characterization, FDI working as a digitizer and as an integrator, was assessed by means of static, dynamic, and time base tests. Typical values of static integral nonlinearity of ±7 ppm, ±3 ppm of 24-h stability, and 108 dB of signal-to-noise-anddistortion ratio at 10 Hz on Nyquist bandwidth of 125 kHz, were surveyed during the integrator working. The actual throughput rate was measured by a specific procedure of PXI bus analysis, by highlighting typical values of 1 MB/s. Finally, the experimental campaign, carried out at CERN facilities of superconducting magnet testing for on-field qualification of FDI, is illustrated. In particular, the FDI was included in a measurement station using also the new generation of fast transducers. The performance of such a station was compared with the one of the previous standard station used in series tests for qualifying LHC magnets. All the results highlight the FDI full capability of acting as the new de-facto standard for high-performance magnetic measurements at CERN and in other high-energy physics research centres

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process