Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications

Advanced correlation filters have been employed in a wide variety of image processing and pattern recognition applications such as automatic target recognition and biometric recognition. Among those, object recognition and tracking have received more attention recently due to their wide range of applications such as autonomous cars, automated surveillance, human-computer interaction, and vehicle navigation.Although digital signal processing has long been used to realize such computational systems, they consume extensive silicon area and power. In fact, computational tasks that require low to moderate signal-to-noise ratios are more efficiently realized in analog than digital. However, analog signal processing has its own caveats. Mainly, noise and offset accumulation which degrades the accuracy, and lack of a scalable and standard input/output interface capable of managing a large number of analog data.Two digitally-interfaced analog correlation filter systems are proposed. While digital interfacing provided a standard and scalable way of communication with pre- and post-processing blocks without undermining the energy efficiency of the system, the multiply-accumulate operations were performed in analog. Moreover, non-volatile floating-gate memories are utilized as storage for coefficients. The proposed systems incorporate techniques to reduce the effects of analog circuit imperfections.The first system implements a 24x57 Gilbert-multiplier-based correlation filter. The I/O interface is implemented with low-power D/A and A/D converters and a correlated double sampling technique is implemented to reduce offset and lowfrequency noise at the output of analog array. The prototype chip occupies an area of 3.23mm2 and demonstrates a 25.2pJ/MAC energy-efficiency at 11.3 kVec/s and 3.2% RMSE.The second system realizes a 24x41 PWM-based correlation filter. Benefiting from a time-domain approach to multiplication, this system eliminates the need for explicit D/A and A/D converters. Careful utilization of clock and available hardware resources in the digital I/O interface, along with application of power management techniques has significantly reduced the circuit complexity and energy consumption of the system. Additionally, programmable transconductance amplifiers are incorporated at the output of the analog array for offset and gain error calibration. The prototype system occupies an area of 0.98mm2 and is expected to achieve an outstanding energy-efficiency of 3.6pJ/MAC at 319kVec/s with 0.28% RMSE

In Situ Automatic Analog Circuit Calibration and Optimization

As semiconductor technology scales down, the variations of active/passive device characteristics after fabrication are getting more and more significant. As a result, many circuits need more accuracy margin to meet minimum accuracy specifications over huge process-voltage-temperature (PVT) variations. Although, overdesigning a circuit is sometimes not a feasible option because of excessive accuracy margin that requires high power consumption and large area. Consequently, calibration/tuning circuits that can automatically detect and compensate the variations have been researched for analog circuits to make better trade-offs among accuracy, power consumption, and area. The first part of this dissertation shows that a newly proposed in situ calibration circuit for a current reference can relax the sharp trade-off between the temperature coefficient accuracy and the power consumption of the current reference. Prototype chips fabricated in a 180 nm CMOS technology generate 1 nA and achieve an average temperature coefficient of 289 ppm/°C and an average line sensitivity of 1.4 %/V with no help from a multiple-temperature trimming. Compared with other state-of-the-art current references that do not need a multiple-temperature trimming, the proposed circuit consumes at least 74% less power, while maintaining similar or higher accuracy. The second part of this dissertation proves that a newly proposed multidimensional in situ analog circuit optimization platform can optimize a Tow-Thomas bandpass biquad. Unlike conventional calibration/tuning approaches, which only handle one or two frequency-domain characteristics, the proposed platform optimizes the power consumption, frequency-, and time-domain characteristics of the biquad to make a better trade-off between the accuracy and the power consumption of the biquad. Simulation results show that this platform reduces the gain-bandwidth product of op-amps in the biquad by 80% while reducing the standard deviations of frequency- and time-domain characteristics by 82%. Measurement results of a prototype chip fabricated in a 180 nm CMOS technology also show that this platform can save maximum 71% of the power consumption of the biquad while the biquad maintains its frequency-domain characteristics: Q, ωO and the gain at ωO

Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D