Analysis and design of a subthreshold CMOS Schmitt trigger circuit

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2017.Nesta tese, o disparador Schmitt (ou Schmitt trigger) CMOS clássico (ST) operando em inversão fraca é analisado. A transferência de tensão DC completa é determinada, incluindo expressões analíticas para as tensões dos nós internos. A transferência de tensão DC resultante do ST apresenta um comportamento contínuo mesmo na presença da histerese. Nesse caso, a característica da tensão de saída entre os limites da histerese é formada por um segmento metaestável, que pode ser explicado em termos das resistências negativas dos subcircuitos NMOS e PMOS do ST. A tensão mínima para o aparecimento da histerese é determinada fazendo-se a análise de pequenos sinais. A análise de pequenos sinais também é utilizada para a estimativa da largura do laço de histerese. É mostrado que a histerese não aparece para tensões de alimentação menores que 75 mV em 300 K. A análise do ST operando como amplificador também foi feita. A razão ótima dos transistores foi determinada com o objetivo de se maximizar o ganho de tensão. A comparação do disparador Schmitt com o inversor CMOS convencional destaca as vantagens e desvantagens de cada um para aplicações de ultra-baixa tensão. Também é mostrado que o ST é teoricamente capaz de operar (com ganho de tensão absoluto ?1) com uma tensão de alimentação tão baixa quanto 31.5 mV, a qual é menor do que o conhecido limite prévio de 36 mV, para o inversor convencional. Como amplificador, o ST possui ganho de tensão absoluto consideravelmente maior que o inversor convencional na mesma tensão de alimentação. Três circuitos integrados foram projetados e fabricados para estudar o comportamento do ST com tensões de alimentação entre 50 mV e 1000 mV.Abstract : In this thesis, the classical CMOS Schmitt trigger (ST) operating in weak inversion is analyzed. The complete DC voltage transfer characteristic is determined, including analytical expressions for the internal node voltage. The resulting voltage transfer characteristic of the ST presents a continuous output behavior even when hysteresis is present. In this case, the output voltage characteristic between the hysteresis limits is formed by a metastable segment, which can be explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. The minimum supply voltage at which hysteresis appears is determined carrying out small-signal analysis, which is also used to estimate the hysteresis width. It is shown that hysteresis does not appear for supply voltages lower than 75 mV at 300 K. The analysis of the ST operating as a voltage amplifier was also carried out. Optimum transistor ratios were determined aiming at voltage gain maximization. The comparison of the ST with the standard CMOS inverter highlights the relative benefits and drawbacks of each one in ULV applications. It is also shown that the ST is theoretically capable of operating (voltage gain ?1) at a supply voltage as low as 31.5 mV, which is lower than the well-known limit of 36 mV, for the standard CMOS inverter. As an amplifier, the ST shows considerable higher absolute voltage gains than those showed by the conventional inverter at the same supply voltages. Three test chips were designed and fabricated to study the operation of the ST at supply voltages between 50 mV and 1000 mV

Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks

Multilayered artificial neural networks (ANN) have found widespread utility in classification and recognition applications. The scale and complexity of such networks together with the inadequacies of general purpose computing platforms have led to a significant interest in the development of efficient hardware implementations. In this work, we focus on designing energy efficient on-chip storage for the synaptic weights. In order to minimize the power consumption of typical digital CMOS implementations of such large-scale networks, the digital neurons could be operated reliably at scaled voltages by reducing the clock frequency. On the contrary, the on-chip synaptic storage designed using a conventional 6T SRAM is susceptible to bitcell failures at reduced voltages. However, the intrinsic error resiliency of NNs to small synaptic weight perturbations enables us to scale the operating voltage of the 6TSRAM. Our analysis on a widely used digit recognition dataset indicates that the voltage can be scaled by 200mV from the nominal operating voltage (950mV) for practically no loss (less than 0.5%) in accuracy (22nm predictive technology). Scaling beyond that causes substantial performance degradation owing to increased probability of failures in the MSBs of the synaptic weights. We, therefore propose a significance driven hybrid 8T-6T SRAM, wherein the sensitive MSBs are stored in 8T bitcells that are robust at scaled voltages due to decoupled read and write paths. In an effort to further minimize the area penalty, we present a synaptic-sensitivity driven hybrid memory architecture consisting of multiple 8T-6T SRAM banks. Our circuit to system-level simulation framework shows that the proposed synaptic-sensitivity driven architecture provides a 30.91% reduction in the memory access power with a 10.41% area overhead, for less than 1% loss in the classification accuracy.Comment: Accepted in Design, Automation and Test in Europe 2016 conference (DATE-2016

Low Voltage CMOS Schmitt Trigger In 0.18μm Technology

This paper presents the effect of source voltage on performance of proposed Schmitt Trigger circuit. The proposed circuit was designed based on Conventional Schmitt Trigger by manipulating the arrangement of transistors and the width-length ratio. The simulation results have been carried out based on Mentor Graphics software in term of propagation delay. The circuit layout has been designed and checked by using design rule check (DRC) and layout versus schematic (LVS) method. From these results, the proposed full swing CMOS Schmitt Trigger was able to operate at low voltage (0.8V-1.5V

Ultra-low Power FinFET SRAM Cell with improved stability suitable for low power applications

In this paper, a new 11T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at sub-threshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV. At sub-threshold operation also it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Also, impact of process variation on cell stability is discussed

A Technique for Designing Variation Resilient Subthreshold Sram Cell

This paper presents a technique for designing a variability aware subthreshold SRAM cell. The architecture of the proposed cell is similar to the standard read-decoupled 8-transistor (RD8T) SRAM cell with the exception that the access FETS are replaced with transmission gates (TGs). In this work, various design metrics are assessed and compared with RD8T SRAM cell. The proposed design offers 2.14× and 1.75× improvement in TRA (read access time) and TWA (write access time) respectively compared with RD8T. It proves its robustness against process variations by featuring narrower spread in TRA distribution (2.35×) and TWA distribution (3.79×) compared with RD8T. The proposed bitcell offers 1.16× higher read current (IREAD) and 1.64× lower bitline leakage current (ILEAK) respectively compared with RD8T. It also shows its robustness by offering 1.34× (1.58×) tighter spread in IREAD (ILEAK) compared with RD8T. It exhibits 1.42× larger IREAD to ILEAK ratio. It shows 2.2× higher frequency @ 250 mV with read bitline capacitance of 10 fF. Besides, the proposed bitcell achieves same read stability and write-ability as that of RD8T at the cost of 3 extra transistors. The leakage power of the proposed design is close to that of RD8T.   ABSTRAK: Kertas kerja ini membentangkan teknik merekabentuk sel bawah ambang SRAM yang bolehubah. Senibina sel yang dicadangkan adalah sama dengan sel SRAM 8-transistor (RD8T) “pisahan-bacaan” piawai kecuali FET akses  digantikan dengan sel pintu transmisi (TGs). Di dalam kajian ini, beberapa metrik rekabentuk dinilai dan dibandingkan dengan sel RD8T SRAM. Rekabentuk yang dicadangkan menawarkan  peningkatan 2.14× dan 1.75×  dalam TRA (masa akses baca) dan TWA (masa akses tulis) berbanding dengan RD8T. Ia membuktikan kekukuhan variasi proses dengan menampilkan tebaran yang lebih sempit dalam pengagihan TRA (2.35 ×) dan pengagihan TWA (3.79 ×) berbanding dengan RD8T. Sel-Bit yang dicadangkan mempunyai arus baca 1.16 × lebih tinggi  (IREAD) dan arus bocor bitline 1.64 × lebih rendah (ILEAK) berbanding dengan RD8T. Ia juga membuktikan kekukuhan dengan menawarkan 1.34 × (1.58 ×) penyebaran sempit di IREAD (ILEAK) berbanding dengan RD8T dan nisbah IREAD / ILEAK 1.42 × lebih besar. Ia menunjukkan kekerapan 2.2 × lebih tinggi pada 250 mV dengan kemuatan membaca bitline sebanyak 10 fF. Selain itu, sel bit yang dicadangkan mencapai kestabilan membaca dan keupayaan menulis yang sama seperti RD8T dengan kos tambahan 3 transistor. Kebocoran kuasa  rekabentuk yang dicadangkan hampir sama dengan RD8T. KEYWORDS: variability; robust, subthreshold; random dopant fluctuation (RDF); read static noise margin (RSNM); write static noise margin (WSNM)

A sub-threshold differential cmos schmitt trigger with adjustable hysteresis based on body bias technique

This paper presents a sub-threshold differential CMOS Schmitt trigger with tunable hysteresis, which can be used to enhance the noise immunity of low-power electronic systems. By exploiting the body bias technique to the positive feedback transistors, the hysteresis of the proposed Schmitt trigger is generated, and it can be adjusted by the applied bias voltage to the bulk terminal of the utilized PMOS transistors. The principle of operation and the main formulas of the proposed circuit are discussed. The circuit is designed in a 0.18-μm standard CMOS process with a 0.6 V power supply. Post-layout simulation results show that the hysteresis width of the Schmitt trigger can be adjusted from 45.5 mV to 162 mV where the ratio of the hysteresis width variation to supply voltage is 19.4%. This circuit consumes 10.52 × 7.91 μm2 of silicon area, and its power consumption is only 1.38 μW, which makes it a suitable candidate for low-power applications such as portable electronic, biomedical, and bio-implantable systems

Ultra-low Voltage Digital Circuits and Extreme Temperature Electronics Design

Certain applications require digital electronics to operate under extreme conditions e.g., large swings in ambient temperature, very low supply voltage, high radiation. Such applications include sensor networks, wearable electronics, unmanned aerial vehicles, spacecraft, and energyharvesting systems. This dissertation splits into two projects that study digital electronics supplied by ultra-low voltages and build an electronic system for extreme temperatures. The first project introduces techniques that improve circuit reliability at deep subthreshold voltages as well as determine the minimum required supply voltage. These techniques address digital electronic design at several levels: the physical process, gate design, and system architecture. This dissertation analyzes a silicon-on-insulator process, Schmitt-trigger gate design, and asynchronous logic at supply voltages lower than 100 millivolts. The second project describes construction of a sensor digital controller for the lunar environment. Parts of the digital controller are an asynchronous 8031 microprocessor that is compatible with synchronous logic, memory with error detection and correction, and a robust network interface. The digitial sensor ASIC is fabricated on a silicon-germanium process and built with cells optimized for extreme temperatures