Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Soft-Error Resilience Framework For Reliable and Energy-Efficient CMOS Logic and Spintronic Memory Architectures

The revolution in chip manufacturing processes spanning five decades has proliferated high performance and energy-efficient nano-electronic devices across all aspects of daily life. In recent years, CMOS technology scaling has realized billions of transistors within large-scale VLSI chips to elevate performance. However, these advancements have also continually augmented the impact of Single-Event Transient (SET) and Single-Event Upset (SEU) occurrences which precipitate a range of Soft-Error (SE) dependability issues. Consequently, soft-error mitigation techniques have become essential to improve systems\u27 reliability. Herein, first, we proposed optimized soft-error resilience designs to improve robustness of sub-micron computing systems. The proposed approaches were developed to deliver energy-efficiency and tolerate double/multiple errors simultaneously while incurring acceptable speed performance degradation compared to the prior work. Secondly, the impact of Process Variation (PV) at the Near-Threshold Voltage (NTV) region on redundancy-based SE-mitigation approaches for High-Performance Computing (HPC) systems was investigated to highlight the approach that can realize favorable attributes, such as reduced critical datapath delay variation and low speed degradation. Finally, recently, spin-based devices have been widely used to design Non-Volatile (NV) elements such as NV latches and flip-flops, which can be leveraged in normally-off computing architectures for Internet-of-Things (IoT) and energy-harvesting-powered applications. Thus, in the last portion of this dissertation, we design and evaluate for soft-error resilience NV-latching circuits that can achieve intriguing features, such as low energy consumption, high computing performance, and superior soft errors tolerance, i.e., concurrently able to tolerate Multiple Node Upset (MNU), to potentially become a mainstream solution for the aerospace and avionic nanoelectronics. Together, these objectives cooperate to increase energy-efficiency and soft errors mitigation resiliency of larger-scale emerging NV latching circuits within iso-energy constraints. In summary, addressing these reliability concerns is paramount to successful deployment of future reliable and energy-efficient CMOS logic and spintronic memory architectures with deeply-scaled devices operating at low-voltages

A flexible single-step 3D nanolithography approach via local anodic oxidation : theoretical and experimental studies

The field of nanotechnology has experienced rapid growth in recent years, fuelled by the increasing need for high-performance next-generation nano/quantum devices/products possessing 3D nanostructures with sub-10 nm feature sizes. As a result, there is a high demand for a new flexible nanofabrication technique capable of generating various 3D nanostructures with high precision and efficiency. Local anodic oxidation (LAO) nanolithography is a promising nanofabrication technique for the in-lab prototyping of nanoproducts due to its high precision, low environmental requirement, and ease of use. However, challenges remain with current LAO nanofabrication techniques to meet the processing demands of next-generation nanoproducts. These challenges include limited throughput, high defect rates, and inflexibility in generating various nanostructures. Consequently, the existing 3D LAO nanofabrication methods suffer from high costs and inefficiencies. Addressing these challenges is crucial for advancing the capabilities of LAO nanolithography and unlocking its full potential in nanofabrication. In this thesis, a novel flexible single-step nanofabrication approach was developed to generate diverse 3D nanostructures with sub-10 nm feature sizes through pulse-modulated LAO nanolithography. Compared with other tool and condition control methods, pulse modulation is easier to achieve with precise tunability, enabling flexible, high-precision, and cost-effective 3D nanofabrication. A clear and in-depth understanding of the manufacturing mechanisms at the atomic and molecular scales is crucial in determining the influencing factors during the manufacturing process. This thesis thus first used the reactive force field (ReaxFF) molecular dynamics simulation method to investigate the reaction mechanisms of the LAO process. A comprehensive analysis of bonding, molecular, and charge indicates that the bias-induced oxidation led mainly to the creation of Si–O–Si bonds in the oxide film and the consumption of H2O. In contrast, the oxidised surface’s chemical composition remained unchanged during the bias-induced oxidation process. In addition, parametric studies further revealed the dependence of electric field strength and humidity on the bias-induced oxidation process and their respective influencing mechanisms. A good agreement was achieved through qualitative comparison between simulation and experimental results. Secondly, this thesis proposed a new pulse-modulated LAO nanolithography approach to realise flexible and efficient fabrication of various 3D nanostructures. The process was designed on the principle that the amplitude or width of the pulse can control the lateral and vertical growth of each nanodot while the tuning of pulse periods can determine the position of each nanodot based on certain tip scan speeds and trajectories. Feasibility tests were conducted on an atomic force microscope (AFM) to demonstrate the capability of this approach in fabricating various nanostructures with the minimum linewidth at sub-10 nm and height variations at sub-nm. Finally, nanofabrication experiments were conducted to investigate the capabilities of pulse-modulated LAO nanolithography in achieving flexible, accurate, and efficient fabrication of 3D nanostructures. Based on the systematic parametric study on the effects of pulse period, amplitude, and width through the LAO experiment, a process model was developed to provide a clear and detailed interpretation of the nanofabrication process. This model links the geometry of 3D nanostructures with arrays of pulse periods, amplitudes, and widths, allowing for active control of the LAO process. The fabrication of several 3D nanostructures was experimentally validated by comparing the fabricated and predicted results, demonstrating good agreement. The fabricated three-dimensional curved surface could achieve the average form accuracy and precision at sub-nm levels. Higher efficiency was achieved by using a high scan rate, enabling the creation of a nanoscale lens structure consisting of four thousand nanodots within 50 seconds. The efficiency and accuracy of the proposed flexible single-step nanofabrication approach were, therefore, fully demonstrated.The field of nanotechnology has experienced rapid growth in recent years, fuelled by the increasing need for high-performance next-generation nano/quantum devices/products possessing 3D nanostructures with sub-10 nm feature sizes. As a result, there is a high demand for a new flexible nanofabrication technique capable of generating various 3D nanostructures with high precision and efficiency. Local anodic oxidation (LAO) nanolithography is a promising nanofabrication technique for the in-lab prototyping of nanoproducts due to its high precision, low environmental requirement, and ease of use. However, challenges remain with current LAO nanofabrication techniques to meet the processing demands of next-generation nanoproducts. These challenges include limited throughput, high defect rates, and inflexibility in generating various nanostructures. Consequently, the existing 3D LAO nanofabrication methods suffer from high costs and inefficiencies. Addressing these challenges is crucial for advancing the capabilities of LAO nanolithography and unlocking its full potential in nanofabrication. In this thesis, a novel flexible single-step nanofabrication approach was developed to generate diverse 3D nanostructures with sub-10 nm feature sizes through pulse-modulated LAO nanolithography. Compared with other tool and condition control methods, pulse modulation is easier to achieve with precise tunability, enabling flexible, high-precision, and cost-effective 3D nanofabrication. A clear and in-depth understanding of the manufacturing mechanisms at the atomic and molecular scales is crucial in determining the influencing factors during the manufacturing process. This thesis thus first used the reactive force field (ReaxFF) molecular dynamics simulation method to investigate the reaction mechanisms of the LAO process. A comprehensive analysis of bonding, molecular, and charge indicates that the bias-induced oxidation led mainly to the creation of Si–O–Si bonds in the oxide film and the consumption of H2O. In contrast, the oxidised surface’s chemical composition remained unchanged during the bias-induced oxidation process. In addition, parametric studies further revealed the dependence of electric field strength and humidity on the bias-induced oxidation process and their respective influencing mechanisms. A good agreement was achieved through qualitative comparison between simulation and experimental results. Secondly, this thesis proposed a new pulse-modulated LAO nanolithography approach to realise flexible and efficient fabrication of various 3D nanostructures. The process was designed on the principle that the amplitude or width of the pulse can control the lateral and vertical growth of each nanodot while the tuning of pulse periods can determine the position of each nanodot based on certain tip scan speeds and trajectories. Feasibility tests were conducted on an atomic force microscope (AFM) to demonstrate the capability of this approach in fabricating various nanostructures with the minimum linewidth at sub-10 nm and height variations at sub-nm. Finally, nanofabrication experiments were conducted to investigate the capabilities of pulse-modulated LAO nanolithography in achieving flexible, accurate, and efficient fabrication of 3D nanostructures. Based on the systematic parametric study on the effects of pulse period, amplitude, and width through the LAO experiment, a process model was developed to provide a clear and detailed interpretation of the nanofabrication process. This model links the geometry of 3D nanostructures with arrays of pulse periods, amplitudes, and widths, allowing for active control of the LAO process. The fabrication of several 3D nanostructures was experimentally validated by comparing the fabricated and predicted results, demonstrating good agreement. The fabricated three-dimensional curved surface could achieve the average form accuracy and precision at sub-nm levels. Higher efficiency was achieved by using a high scan rate, enabling the creation of a nanoscale lens structure consisting of four thousand nanodots within 50 seconds. The efficiency and accuracy of the proposed flexible single-step nanofabrication approach were, therefore, fully demonstrated

ULTRARAM™:Design, Modelling, Fabrication and Testing of Ultra-low-power III-V Memory Devices and Arrays

In this thesis, a novel memory based on III-V compound semiconductors is studied, both theoretically and experimentally, with the aim of developing a technology with superior performance capabilities to established and emerging rival memories. This technology is known as ULTRARAM™. The memory concept is based on quantum resonant tunnelling through InAs/AlSb heterostructures, which are engineered to only allow electron tunnelling at precise energy alignment(s) when a bias is applied. The memory device features a floating gate (FG) as the storage medium, where electrons that tunnel through the InAs/AlSb heterostructure are confined in the FG to define the memory logic (0 or 1). The large conduction band offset of the InAs/AlSb heterojunction (2.1 eV) keeps electrons in the FG indefinitely, constituting a non-volatile logic state. Electrons can be removed from the FG via a similar resonant tunnelling process by reversing the voltage polarity. This concept shares similarities with flash memory, however the resonant tunnelling mechanism provides ultra-low-power, low-voltage, high-endurance and high-speed switching capability. The quantum tunnelling junction is studied in detail using the non-equilibrium Green’s function (NEGF) method. Then, Poisson-Schrödinger simulations are used to design a high-contrast readout procedure for the memory using the unusual type-III band-offset of the InAs/GaSb heterojunction. With the theoretical groundwork for the technology laid out, the memory performance is modelled and a high-density ULTRARAM™ memory architecture is proposed for random-access memory applications. Later, NEGF calculations are used for a detailed study of the process tolerances in the tunnelling region required for ULTRARAM™ large-scale wafer manufacture. Using interfacial misfit array growth techniques, III-V layers (InAs, AlSb and GaSb) for ULTRARAM™ were successfully implemented on both GaAs and Si substrates. Single devices and 2×2 arrays were then fabricated using a top-down processing approach. The memories demonstrated outstanding memory performance on both substrate materials at 10, 20 and 50 µm gate lengths at room temperature. Non-volatile switching was obtained with ≤ 2.5 V pulses, corresponding to a switching energy per unit area that is lower than DRAM and flash by factors of 100 and 1000 respectively. Memory logic was retained for over 24 hours whilst undergoing over 10^6 readout operations. Analysis of the retention data suggests a storage time exceeding 1000 years. Devices showed promising durability results, enduring over 10^7 cycles without degradation, at least two orders of magnitude improvement over flash memory. Switching of the cell’s logic was possible at 500 µs pulse durations for a 20 µm gate length, suggesting a subns switching time if scaled to modern-day feature sizes. The proposed half-voltage architecture is shown to operate in principle, where the memory state is preserved during a disturbance test of > 10^5 half-cycles. With regard to the device physics, these findings point towards ULTRARAM™ as a universal memory candidate. The path towards future commercial viability relies on process development for aggressive device and array-size scaling and implementation on larger Si wafe

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before