ESD circuit design and measurement techniques

Part 1 of this thesis presents a method to measure sub-nanosecond reverse recovery in wafer-level test structures. The setup uses a transmission line pulse generator with a time domain through connection to measure the device under test current. The setup is then used to measure reverse recovery in a 65 nm CMOS ESD diode, and it is found that a quasi-static compact model does not accurately describe the observed transient. A non-quasi-static charge control model is used to accurately simulate both the reverse recovery and forward bias behavior. Part 2 of this thesis reports the design and fabrication of an active feedback based high-voltage tolerant power clamp with optimally biased positive and negative feedback to bypass the trade-off between ESD performance and mis-trigger immunity. The circuit was fabricated in 28 nm CMOS, and characterization results show a 70% improvement in failure current over previous designs while maintaining mis-trigger immunity

On-die transient event sensors and system-level ESD testing

System level electrostatic discharge (ESD) testing of electronic products is a critical part of product certification. Test methods were investigated to develop system level ESD simulation models to predict soft-failures in a system with multiple sensors. These methods rely completely on measurements. The model developed was valid only for the linear operation range of devices within the system. These methods were applied to a commercial product and used to rapidly determine when a soft failure would occur. Attaching cables and probes to determine stress voltages and currents within a system, as in the previous study, is time-consuming and can alter the test results. On-chip sensors have been developed which allow the user to avoid using cables and probes and can detect an event along with the level, polarity, and location of a transient event seen at the I/O pad. The sensors were implemented with minimum area consumption and can be implemented within the spacer cell of an I/O pad. Some of the proposed sensors were implemented in a commercial test microcontroller and have been tested to successfully record the event occurrence, location, level, and polarity on that test microcontroller. System level tests were then performed on a pseudo-wearable device using the on-chip sensors. The measurements were successful in capturing the peak disturbance and counting the number of ESD events without the addition of any external measurement equipment. A modification of the sensors was also designed to measure the peak voltage on a trace or pin inside a complex electronic product. The peak current can also be found when the sensor is placed across a transient voltage suppressor with a known I-V curve. The peak level is transmitted wirelessly to a receiver outside the system using frequency-modulated magnetic or electric fields, thus allowing multiple measurements to be made without opening the enclosure or otherwise modifying the system. Simulations demonstrate the sensors can accurately detect the peak transient voltage and transmit the level to an external receiver --Abstract, page iv

Design of Novel Devices and Circuits for Electrostatic Discharge Protection Applications in Advanced Semiconductor Technologies

Electrostatic Discharge (ESD), as a subset of Electrical Overstress (EOS), was reported to be in charge of more than 35% of failure in integrated circuits (ICs). Especially in the manufacturing process, the silicon wafer turns out to be a functional ICs after numerous physical, chemical and mechanical processes, each of which expose the sensitive and fragile ICs to ESD environment. In normal end-user applications, ESD from human and machine handling, surge and spike signals in the power supply, and wrong supplying signals, will probably cause severe damage to the ICs and even the whole systems. Generally, ESD protections are evaluated after wafer and even system fabrication, increasing the development period and cost if the protections cannot meet customer\u27s requirements. Therefore, it is important to design and customize robust and area-efficient ESD protections for the ICs at the early development stage. As the technologies generally scaling down, however, ESD protection clamps remain comparable area consumption in the recent years because they provide the discharging path for the ESD energy which rarely scales down. Diode is the most simple and effective device for ESD protection in ICs, but the usage is significantly limited by its low turn-on voltage. MOS devices can be triggered by a dynamic-triggered RC circuit for IOs operating at low voltage, while the one triggered by a static-triggered network, e.g., zener-resistor circuit or grounded-gate configuration, provides a high trigger voltage for high-voltage applications. However, the relatively low current discharging capability makes MOS devices as the secondary choice. Silicon-controlled rectifier (SCR) has become famous due to its high robustness and area efficiency, compared to diode and MOS. In this dissertation, a comprehensive design methodology for SCR based on simulation and measurement are presented for different advanced commercial technologies. Furthermore, an ESD clamp is designed and verified for the first time for the emerging GaN technology. For the SCR, no matter what modification is going to be made, the first concern when drawing the layout is to determine the layout geometrical style, finger width and finger number. This problem for diode and MOS device were studied in detail, so the same method was usually used in SCR. The research in this dissertation provides a closer look into the metal layout effect to the SCR, finding out the optimized robustness and minimized side-effect can be obtained by using specific layout geometry. Another concern about SCR is the relatively low turn-on speed when the IOs under protection is stressed by ESD pulses having very fast rising time, e.g., CDM and IEC 61000-4-2 pulses. On this occasion a large overshoot voltage is generated and cause damage to internal circuit component like gate oxides of MOS devices. The key determination of turn-on speed of SCR is physically investigated, followed by a novel design on SCR by directly connecting the Anode Gate and Cathode Gate to form internal trigger (DCSCR), with improved performance verified experimentally in this dissertation. The overshoot voltage and trigger voltage of the DCSCR will be significantly reduced, in return a better protection for internal circuit component is offered without scarifying neither area or robustness. Even though two SCR\u27s with single direction of ESD current path can be constructed in reverse parallel to form bidirectional protection to pins, stand-alone bidirectional SCR (BSCR) is always desirable for sake of smaller area. The inherent high trigger voltage of BSCR that only fit in high-voltage technologies is overcome by embedding a PMOS transistor as trigger element, making it highly suitable for low-voltage ESD protection applications. More than that, this modification simultaneously introduces benefits including high robustness and low overshoot voltage. For high voltage pins, however, it presents another story for ESD designs. The high operation voltages require that a high trigger voltage and high holding voltage, so as to reduce the false trigger and latch-up risk. For several capacitive pins, the displacement current induced by a large snapback will cause severe damage to internal circuits. A novel design on SCR is proposed to minimize the snapback with adjustable trigger and holding voltage. Thanks to the additional a PIN diode, the similar high robustness and stable thermal leakage performance to SCR is maintained. For academic purpose of ESD design, it is always difficult to obtain the complete process deck in TCAD simulation because those information are highly confidential to the companies. Another challenge of using TCAD is the difficulty of maintaining the accuracy of physics models and predicting the performance of the other structures. In this dissertation a TCAD-aid ESD design methodology is used to evaluate ESD performance before the silicon shuttle. GaN is a promising material for high-voltage high-power RF application compared to the GaAs. However, distinct from GaAs, the leaky problem of the schottky junction and the lack of choice of passive/active components in GaN technology limit the ESD protection design, which will be discussed in this dissertation. However, a promising ESD protection clamp is finally developed based on depletion-mode pHEMT with adjustable trigger voltage, reasonable leakage current and high robustness