ハードウェアリソースの高稼働率化に基づく細粒度多値リコンフィギャラブルVLSIアーキテクチャ

Tohoku University亀山充隆課

Ultrafast and low-energy switching in voltage-controlled elliptical pMTJ

Switching magnetization in a perpendicular magnetic tunnel junction (pMTJ) via voltage controlled magnetic anisotropy (VCMA) has shown the potential to markedly reduce the switching energy. However, the requirement of an external magnetic field poses a critical bottleneck for its practical applications. In this work, we propose an elliptical-shaped pMTJ to eliminate the requirement of providing an external field by an additional circuit. We demonstrate that a 10 nm thick in-plane magnetized bias layer (BL) separated by a metallic spacer of 3 nm from the free layer (FL) can be engineered within the MTJ stack to provide the 50 mT bias magnetic field for switching. By conducting macrospin simulation, we find that a fast switching in 0.38 ns with energy consumption as low as 0.3 fJ at a voltage of 1.6 V can be achieved. Furthermore, we study the phase diagram of switching probability, showing that a pulse duration margin of 0.15 ns is obtained and a low-voltage operation (~ 1 V) is favored. Finally, the MTJ scalability is considered, and it is found that scaling-down may not be appealing in terms of both the energy consumption and the switching time for the precession based VCMA switching.Comment: There are 28 pages and 5 figure

A RISC-V based medical implantable SOC for high voltage a current tissue stimulus

A RISC-V based System on Chip (SoC) for high voltage and current tissue stimulus, targeting implantable medical devices, is presented. The circuit is designed in a 0.18μm HV-CMOS process, including the RISC-V 32RVI based microcontroller core, called Siwa —which includes SPI, UART and GPIO interfaces, a packet-based bus and memory controller, and 8kB SRAM—, combined with several biological tissue stimulus and sensing circuits. The complete test chip (analog+RISC-V) occupies a 5mm2 area but only 0.82mm2 correspond to the RISCV micro-controller, which operates up to 20MHz, with average energy needs of less than 48 pJ/cycle (3pJ STD), and for which several reliability and safety issues were considered.Agencia Nacional de Investigación e Innovació

Impact of TFET unidirectionality and ambipolarity on the performance of 6T SRAM cells

We use mixed device-circuit simulations to predict the performance of 6T static RAM (SRAM) cells implemented with tunnel-FETs (TFETs). Idealized template devices are used to assess the impact of device unidirectionality, which is inherent to TFETs and identify the most promising configuration for the access transistors. The same template devices are used to investigate the $ extV- m DD range, where TFETs may be advantageous compared to conventional CMOS. The impact of device ambipolarity on SRAM operation is also analyzed. Realistic device templates extracted from experimental data of fabricated state-of-the-art silicon pTFET are then used to estimate the performance gap between the simulation of idealized TFETs and the best experimental implementations

A Read-Decoupled Gated-Ground SRAM Architecture for Low-Power Embedded Memories

In order to meet the incessantly growing demand of performance, the amount of embedded or on-chip memory in microprocessors and systems-on-chip (SOC) is increasing. As much as 70% of the chip area is now dedicated to the embedded memory, which is primarily realized by the static random access memory (SRAM). Because of the large size of the SRAM, its yield and leakage power consumption dominate the overall yield and leakage power consumption of the chip. However, as the CMOS technology continues to scale in the sub-65 nanometer regime to reduce the transistor cost and the dynamic power, it poses a number of challenges on the SRAM design. In this thesis, we address these challenges and propose cell-level and architecture level solutions to increase the yield and reduce the leakage power consumption of the SRAM in nanoscale CMOS technologies. The conventional six transistor (6T) SRAM cell inherently suffers from a trade-off between the read stability and write-ability because of using the same bit line pair for both the read and write operations. An optimum design at a given process and voltage condition is a key to ensuring the yield and reliability of the SRAM. However, with technology scaling, process-induced variations in the transistor dimensions and electrical parameters coupled with variation in the operating conditions make it difficult to achieve a reasonably high yield. In this work, a gated SRAM architecture based on a seven transistor (7T) SRAM bit-cell is proposed to address these concerns. The proposed cell decouples the read bit line from the write bit lines. As a result, the storage node is not affected by any read induced noise during the read operation. Consequently, the proposed cell shows higher data stability and yield under varying process, voltage, and temperature (PVT) conditions. A single-ended sense amplifier is also presented to read from the proposed 7T cell while a unique write mechanism is used to reduce the write power to less than half of the write power of the conventional 6T cell. The proposed cell consumes similar silicon area and leakage power as the 6T cell when laid out and simulated using a commercial 65-nm CMOS technology. However, as much as 77% reduction in leakage power can be achieved by coupling the 7T cell with the column virtual grounding (CVG) technique, where a non-zero voltage is applied to the source terminals of driver NMOS transistors in the cell. The CVG technique also enables implementing multiple words per row, which is a key requirement for memories to avoid multiple-bit data upset in the event of radiation induced single event upset or soft error. In addition, the proposed cell inherently has a 30% larger soft error critical charge, making its soft error rate (SER) less than the half of that of the 6T cell

Circuit designs for low-power and SEU-hardened systems

The desire to have smaller and faster portable devices is one of the primary motivations for technology scaling. Though advancements in device physics are moving at a very good pace, they might not be aggressive enough for now-a-day technology scaling trends. As a result, the MOS devices used for present day integrated circuits are pushed to the limit in terms of performance, power consumption and robustness, which are the most critical criteria for almost all applications. Secondly, technology advancements have led to design of complex chips with increasing chip densities and higher operating speeds. The design of such high performance complex chips (microprocessors, digital signal processors, etc) has massively increased the power dissipation and, as a result, the operating temperatures of these integrated circuits. In addition, due to the aggressive technology scaling the heat withstanding capabilities of the circuits is reducing, thereby increasing the cost of packaging and heat sink units. This led to the increase in prominence for smarter and more robust low-power circuit and system designs. Apart from power consumption, another criterion affected by technology scaling is robustness of the design, particularly for critical applications (security, medical, finance, etc). Thus, the need for error free or error immune designs. Until recently, radiation effects were a major concern in space applications only. With technology scaling reaching nanometer level, terrestrial radiation has become a growing concern. As a result Single Event Upsets (SEUs) have become a major challenge to robust designs. Single event upset is a temporary change in the state of a device due to a particle strike (usually from the radiation belts or from cosmic rays) which may manifest as an error at the output. This thesis proposes a novel method for adaptive digital designs to efficiently work with the lowest possible power consumption. This new technique improves options in performance, robustness and power. The thesis also proposes a new dual data rate flipflop, which reduces the necessary clock speed by half, drastically reducing the power consumption. This new dual data rate flip-flop design culminates in a proposed unique radiation hardened dual data rate flip-flop, Firebird\u27. Firebird offers a valuable addition to the future circuit designs, especially with the increasing importance of the Single Event Upsets (SEUs) and power dissipation with technology scaling.\u2

高密度・高速動作可能なSTT-MRAMへ向けたp-MTJのスイッチング過渡現象とアレイ設計指針に関する研究

Tohoku University遠藤哲郎課