64 research outputs found
Slender PUF Protocol: A lightweight, robust, and secure authentication by substring matching
We introduce Slender PUF protocol, an efficient
and secure method to authenticate the responses
generated from a Strong Physical Unclonable Function
(PUF). The new method is lightweight, and suitable for
energy constrained platforms such as ultra-low power embedded
systems for use in identification and authentication
applications. The proposed protocol does not follow the
classic paradigm of exposing the full PUF responses (or
a transformation of the full string of responses) on the
communication channel. Instead, random subsets of the
responses are revealed and sent for authentication. The
response patterns are used for authenticating the prover
device with a very high probability.We perform a thorough
analysis of the method’s resiliency to various attacks
which guides adjustment of our protocol parameters for
an efficient and secure implementation. We demonstrate
that Slender PUF protocol, if carefully designed, will be
resilient against all known machine learning attacks. In
addition, it has the great advantage of an inbuilt PUF error
tolerance. Thus, Slender PUF protocol is lightweight and
does not require costly additional error correction, fuzzy
extractors, and hash modules suggested in most previously
known PUF-based robust authentication techniques. The
low overhead and practicality of the protocol are confirmed
by a set of hardware implementation and evaluations
FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis
Field-programmable gate arrays (FPGAs) have firmly established themselves as dynamic platforms for the implementation of physical unclonable functions (PUFs). Their intrinsic reconfigurability and profound implications for enhancing hardware security make them an invaluable asset in this realm. This groundbreaking study not only dives deep into the universe of FPGA-based PUF designs but also offers a comprehensive overview coupled with a discerning comparative analysis. PUFs are the bedrock of device authentication and key generation and the fortification of secure cryptographic protocols. Unleashing the potential of FPGA technology expands the horizons of PUF integration across diverse hardware systems. We set out to understand the fundamental ideas behind PUF and how crucially important it is to current security paradigms. Different FPGA-based PUF solutions, including static, dynamic, and hybrid systems, are closely examined. Each design paradigm is painstakingly examined to reveal its special qualities, functional nuances, and weaknesses. We closely assess a variety of performance metrics, including those related to distinctiveness, reliability, and resilience against hostile threats. We compare various FPGA-based PUF systems against one another to expose their unique advantages and disadvantages. This study provides system designers and security professionals with the crucial information they need to choose the best PUF design for their particular applications. Our paper provides a comprehensive view of the functionality, security capabilities, and prospective applications of FPGA-based PUF systems. The depth of knowledge gained from this research advances the field of hardware security, enabling security practitioners, researchers, and designers to make wise decisions when deciding on and implementing FPGA-based PUF solutions.publishedVersio
A Deep Analysis of Hybrid-Multikey-PUF
Unique key generation is essential for encryption purposes between Internet
of Things (IoT) devices. To produce a unique key for this encryption, Physical
Unclonable Functions (PUFs) might be employed. Also, the Random Number
Generator (RNG) is used in many different domains; nonetheless, security is one
of the most important areas that require the best RNG. In this article, We
investigate the quality of random numbers generated by Physical Unclonable
Functions (PUFs). We have analyzed three Figures of Merit (FoMs), Uniqueness,
Randomness, and Reliability of PUFs implemented on different FPGAs. In our
experiments, we have operated the test devices at different temperatures
(20{\deg}F, 40{\deg}F, 60{\deg}F, 80{\deg}F, 120{\deg}F, 140{\deg}F). In the
PUF that we have analyzed, the key is generated in 1 second on average. We also
have analyzed and described the essential properties of random number generator
that is most vital considering things to secure our Internet of Things(IoT)
devices.Comment: 6,8th IEEE World Forum on Internet of Things (IEEE WFIoT2022
Lightweight Silicon-based Security: Concept, Implementations, and Protocols
Advancement in cryptography over the past few decades has enabled a spectrum of security mechanisms and protocols for many applications. Despite the algorithmic security of classic cryptography, there are limitations in application and implementation of standard security methods in ultra-low energy and resource constrained
systems. In addition, implementations of standard cryptographic methods can be
prone to physical attacks that involve hardware level invasive or non-invasive attacks.
Physical unclonable functions (PUFs) provide a complimentary security paradigm for a number of application spaces where classic cryptography has shown to be inefficient or inadequate for the above reasons. PUFs rely on intrinsic device-dependent
physical variation at the microscopic scale. Physical variation results from imperfection
and random fluctuations during the manufacturing process which impact each device’s characteristics in a unique way. PUFs at the circuit level amplify and capture
variation in electrical characteristics to derive and establish a unique device-dependent
challenge-response mapping.
Prior to this work, PUF implementations were unsuitable for low power applications
and vulnerable to wide range of security attacks. This doctoral thesis presents a coherent framework to derive formal requirements to design architectures and protocols
for PUFs. To the best of our knowledge, this is the first comprehensive work that
introduces and integrates these pieces together. The contributions include an introduction
of structural requirements and metrics to classify and evaluate PUFs, design
of novel architectures to fulfill these requirements, implementation and evaluation of
the proposed architectures, and integration into real-world security protocols.
First, I formally define and derive a new set of fundamental requirements and
properties for PUFs. This work is the first attempt to provide structural requirements
and guideline for design of PUF architectures. Moreover, a suite of statistical properties of PUF responses and metrics are introduced to evaluate PUFs.
Second, using the proposed requirements, new and efficient PUF architectures are
designed and implemented on both analog and digital platforms. In this work, the
most power efficient and smallest PUF known to date is designed and implemented on ASICs that exploits analog variation in sub-threshold leakage currents of MOS
devices. On the digital platform, the first successful implementation of Arbiter-PUF on FPGA was accomplished in this work after years of unsuccessful attempts by the research community. I introduced a programmable delay tuning mechanism with pico-second resolution which serves as a key component in implementation of the
Arbiter-PUF on FPGA. Full performance analysis and comparison is carried out through comprehensive device simulations as well as measurements performed on a
population of FPGA devices.
Finally, I present the design of low-overhead and secure protocols using PUFs for integration in lightweight identification and authentication applications. The new protocols are designed with elegant simplicity to avoid the use of heavy hash operations
or any error correction. The first protocol uses a time bound on the authentication process while second uses a pattern-matching index-based method to thwart reverseengineering
and machine learning attacks. Using machine learning methods during
the commissioning phase, a compact representation of PUF is derived and stored in a database for authentication
Compact Field Programmable Gate Array Based Physical Unclonable Functions Circuits
The Physical Unclonable Functions (PUFs) is a candidate to provide a secure solid root source for identification and authentication applications. It is precious for FPGA-based systems, as FPGA designs are vulnerable to IP thefts and cloning. Ideally, the PUFs should have strong random variations from one chip to another, and thus each PUF is unique and hard to replicate. Also, the PUFs should be stable over time so that the same challenge bits always yield the same result. Correspondingly, one of the major challenges for FPGA-based PUFs is the difficulty of avoiding systematic bias in the integrated circuits but also pulling out consistent characteristics as the PUF at the same time. This thesis discusses several compact PUF structures relying on programmable delay lines (PDLs) and our novel intertwined programmable delays (IPD). We explore the strategy to extract the genuinely random PUF from these structures by minimizing the systematic biases. Yet, our methods still maintain very high reliability. Furthermore, our proposed designs, especially the TERO-based PUFs, show promising resilience to machine learning (ML) attacks. We also suggest the bit-bias metric to estimate PUF’s complexity quickly
- …