Ultra-Thin Chip Package (UTCP) and stretchable circuit technologies for wearable ECG system

A comfortable, wearable wireless ECG monitoring system is proposed. The device is realized using the combination of two proprietary advanced technologies for electronic packaging and interconnection : the UTCP (Ultra-Thin Chip Package) technology and the SMI (Stretchable Mould Interconnect) technology for elastic and stretchable circuits. Introduction of these technologies results in small fully functional devices, exhibiting a significant increase in user comfort compared to devices fabricated with more conventional packaging and interconnection technologies

A contact lens with built-in display: science fiction or not?

Recent progress in microsystems integration technology such as ultra-thin chip packaging, stretchable interconnections, thin-film batteries and organic photovoltaics makes it feasible to incorporate various electronic components and transducers in extremely confined spaces and inside flexible or conformable objects. Can this ultimately lead to a genuine display in a contact lens? The major outstanding issues are reviewed

Ultra-thin chips for high-performance flexible electronics

Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics

Insulation lifetime improvement of polyimide thin film neural implants

Objective. This work deals with studying and improving the insulation lifetime of polyimideinsulated thin film neural implants, or related polyimide-based medical implants. Approach. The evolution of the leak impedance of insulated conductors was investigated in saline water at 40 °C. The fabrication process as commonly found in literature for polyimide/platinum/ polyimide microelectrode arrays was compared with three possible improvements: one based on lowering the curing temperature of the lower layer, one based on chemical activation and one based on an additional plasma activation step. Main results. The lower curing temperature process was found to yield a 7.5-fold improved lifetime compared with the state of the art process. Also, the leak impedances found after soak testing are an order of magnitude higher compared to the standard process. Significance. By improving the lifetime and insulation impedance of polyimide insulation with one order of magnitude, this work increases the applicability of polyimide in chronic thin film neural implants considerably.status: publishe

New Techniques for Multi-Channel Biosignal Acquisition and Low-Power, Low-Resistance-Measurement Systems

Dense electrical recording of biosignals has been developed to provide spatial resolution and precise temporal information for health monitoring, diagnostics, and clinical research. However, more electrodes require more wires, and wiring density quickly becomes a limiting factor. To break this bottleneck, we proposed a frequency-division multiplexing (FDM) based architecture for multi-channel acquisition systems. In this final exam, I present two applications that make use of this FDM technique. The first is an FDM-based multi-channel electromyography (EMG) acquisition system, which demonstrates that the FDM system not only reduces wire count, but also mitigates the effect of low frequency motion artifacts and 50/60 Hz mains interference introduced in the wire. An FDM-based four-channel EMG recording is demonstrated, while carrying all channels over a 3-wire interface, and the system achieves an attenuation of low-frequency cable motion artifacts by 15X an! d 60Hz mains noise coupled in the cable by 62X. A second application that forms the basis of my current research effort is an FDM-based neural recording system with multiple graphene active electrodes. We demonstrated a two-channel system including graphene FET electrodes, a custom integrated circuit (IC) analog front-end (AFE), and digital demodulation. In related multi-channel sensor work, a growing need for ultra-low-power sensors has driven continuous advancement in read-out circuits for temperature, humidity, and pressure. IC-integrated Wheatstone bridges, commonly used, are efficient for large sensor resistance (5k-500kohm), but measuring small resistance (30,000x smaller nominal sensor resistance

Komponentin liittäminen venyvälle alustalle puettavan elektroniikan sovelluksissa

Wearable electronics is a new growing field of technology. Many companies have introduced wearable electronics applications, mostly related to the fields of fitness or healthcare. The wearable device should be able to be worn unobtrusively and safely. In order to guarantee those the stretchable electronics may be a more suitable option than conventional rigid electronics or even flexible electronics. One way to implement a stretchable electronics circuit is by miniaturizing functional modules to small rigid functional islands. The islands can be mounted on the stretchable substrate by an adhesive and connected to each other with stretchable interconnects. In this thesis, the aim is to manufacture and evaluate adhesive joints of a different kind between the stretchable substrate and the rigid component. First in this thesis, the theoretical background of the stretchable materials, of the adhesives and of the manufacturing processes is studied. For testing the adhesive joints, the test samples with screen-printed interconnects are manufactured. Then the components are mounted on the substrates by adhesives and the initial electrical properties of the samples are measured. After that the uniaxial cyclic stretch test is implemented where the resistances of the samples are measured continuously using 4-point measurements. The one-time elasticity test is implemented only with the best combination of the adhesive and the substrate. In addition in this thesis, a custom-made test setup is designed and executed which aim is to stretch the sample for the same amount in every direction at the same time. The functionality of the setup is evaluated by comparing it with the other test setup. There were two main quality issues related to the screen-printing process. Firstly, the ink cracked on one substrate and secondly, the impurities weakened the quality of the printed traces. Although the measured sheet resistance values of the ink were higher than in the datasheet of the ink was reported they were still sufficient for this thesis. Only the samples that had all the four measurement channels with an initial resistance lower than 110 Ω were accepted to the strain tests. In addition to the adhesive joint, the measurement included also the resistance of the component and of the small parts of the printed wires. During the strain test, the samples were stretched 10 % for 500 times. The variation between the samples was high, even with the samples with the same combination of the adhesive and the substrate. However, one adhesive performed better than the others. Thus, it was used also in the comparison between the test setups. With the custom-made test setup, the samples lost the connection with a lower uniaxial measured extension, so the setup functioned as expected

Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems

The 2021 flexible and printed electronics roadmap

This roadmap includes the perspectives and visions of leading researchers in the key areas of flexible and printable electronics. The covered topics are broadly organized by the device technologies (sections 1–9), fabrication techniques (sections 10–12), and design and modeling approaches (sections 13 and 14) essential to the future development of new applications leveraging flexible electronics (FE). The interdisciplinary nature of this field involves everything from fundamental scientific discoveries to engineering challenges; from design and synthesis of new materials via novel device design to modelling and digital manufacturing of integrated systems. As such, this roadmap aims to serve as a resource on the current status and future challenges in the areas covered by the roadmap and to highlight the breadth and wide-ranging opportunities made available by FE technologies

Ultra-thin silicon technology for tactile sensors

In order to meet the requirements of high performance flexible electronics in fast growing portable consumer electronics, robotics and new fields such as Internet of Things (IoT), new techniques such as electronics based on nanostructures, molecular electronics and quantum electronics have emerged recently. The importance given to the silicon chips with thickness below 50 μm is particularly interesting as this will advance the 3D IC technology as well as open new directions for high-performance flexible electronics. This doctoral thesis focusses on the development of silicon–based ultra-thin chip (UTC) for the next generation flexible electronics. UTCs, on one hand can provide processing speed at par with state-of-the-art CMOS technology, and on the other provide the mechanical flexibility to allow smooth integration on flexible substrates. These development form the motivation behind the work presented in this thesis. As the thickness of any silicon piece decreases, the flexural rigidity decreases. The flexural rigidity is defined as the force couple required to bend a non-rigid structure to a unit curvature, and therefore the flexibility increases. The new approach presented in this thesis for achieving thin silicon exploits existing and well-established silicon infrastructure, process, and design modules. The thin chips of thicknesses ranging between 15 μm – 30 μm, were obtained from processed bulk wafer using anisotropic chemical etching. The thesis also presents thin wafer transfer using two-step transfer printing approach, packaging by lamination or encapsulation between two flexible layerand methods to get the electrical connections out of the chip. The devices realised on the wafer as part of front-end processing, consisted capacitors and transistors, have been tested to analyse the effect of bending on the electrical characteristics. The capacitance of metal-oxide-semiconductor (MOS) capacitors increases by ~5% during bending and similar shift is observed in flatband and threshold voltages. Similarly, the carrier mobility in the channel region of metal-oxide-semiconductor field effect transistor (MOSFET) increases by 9% in tensile bending and decreases by ~5% in compressive bending. The analytical model developed to capture the effect of banding on device performance showed close matching with the experimental results. In order to employ these devices as tactile sensors, two types of piezoelectric materials are investigated, and used in extended gate configuration with the MOSFET. Firstly, a nanocomposite of Poly(vinylidene fluoride-co-trifluoroethylene), P(VDF-TrFE) and barium titanate (BT) was developed. The composite, due to opposite piezo and pyroelectric coefficients of constituents, was able to suppress the sensitivity towards temperature when force and temperature varied together, The sensitivity to force in extended gate configuration was measured to be 630 mV/N, and sensitivity to temperature was 6.57 mV/oC, when it was varied during force application. The process optimisation for sputtering piezoelectric Aluminium Nitride (AlN) was also carried out with many parametric variation. AlN does not require poling to exhibit piezoelectricity and therefore offers an attractive alternative for the piezoelectric layer used in devices such as POSFET (where piezoelectric material is directly deposited over the gate area of MOSFET). The optimised process gave highly orientated columnar structure AlN with piezoelectric coefficient of 5.9 pC/N and when connected in extended gate configuration, a sensitivity (normalised change in drain current per unit force) of 2.65 N-1 was obtained