Toward Brain Area Sensor Wireless Network

RÉSUMÉ De nouvelles approches d'interfaçage neuronal de haute performance sont requises pour les interfaces cerveau-machine (BMI) actuelles. Cela nécessite des capacités d'enregistrement/stimulation performantes en termes de vitesse, qualité et quantité, c’est à dire une bande passante à fréquence plus élevée, une résolution spatiale, un signal sur bruit et une zone plus large pour l'interface avec le cortex cérébral. Dans ce mémoire, nous parlons de l'idée générale proposant une méthode d'interfaçage neuronal qui, en comparaison avec l'électroencéphalographie (EEG), l'électrocorticographie (ECoG) et les méthodes d'interfaçage intracortical conventionnelles à une seule unité, offre de meilleures caractéristiques pour implémenter des IMC plus performants. Les avantages de la nouvelle approche sont 1) une résolution spatiale plus élevée - en dessous dumillimètre, et une qualité de signal plus élevée - en termes de rapport signal sur bruit et de contenu fréquentiel - comparé aux méthodes EEG et ECoG; 2) un caractère moins invasif que l'ECoG où l'enlèvement du crâne sous une opération d'enregistrement / stimulation est nécessaire; 3) une plus grande faisabilité de la libre circulation du patient à l'étude - par rapport aux deux méthodes EEG et ECoG où de nombreux fils sont connectés au patient en cours d'opération; 4) une utilisation à long terme puisque l'interface implantable est sans fil - par rapport aux deux méthodes EEG et ECoG qui offrent des temps limités de fonctionnement. Nous présentons l'architecture d'un réseau sans fil de microsystèmes implantables, que nous appelons Brain Area Sensor NETwork (Brain-ASNET). Il y a deux défis principaux dans la réalisation du projet Brain-ASNET. 1) la conception et la mise en oeuvre d'un émetteur-récepteur RF de faible consommation compatible avec la puce de capteurs de réseau implantable, et, 2) la conception d'un protocole de réseau de capteurs sans fil (WSN) ad-hoc économe en énergie. Dans ce mémoire, nous présentons un protocole de réseau ad-hoc économe en énergie pour le réseau désiré, ainsi qu'un procédé pour surmonter le problème de la longueur de paquet variable causé par le processus de remplissage de bit dans le protocole HDLC standard. Le protocole adhoc proposé conçu pour Brain-ASNET présente une meilleure efficacité énergétique par rapport aux protocoles standards tels que ZigBee, Bluetooth et Wi-Fi ainsi que des protocoles ad-hoc de pointe. Le protocole a été conçu et testé par MATLAB et Simulink.----------ABSTRACT New high-performance neural interfacing approaches are demanded for today’s Brain-Machine Interfaces (BMI). This requires high-performance recording/stimulation capabilities in terms of speed, quality, and quantity, i.e. higher frequency bandwidth, spatial resolution, signal-to-noise, and wider area to interface with the cerebral cortex. In this thesis, we talk about the general proposed idea of a neural interfacing method which in comparison with Electroencephalography (EEG), Electrocorticography (ECoG), and, conventional Single-Unit Intracortical neural interfacing methods offers better features to implement higher-performance BMIs. The new approach advantages are 1) higher spatial resolution – down to sub-millimeter, and higher signal quality − in terms of signal-to-noise ratio and frequency content − compared to both EEG and ECoG methods. 2) being less invasive than ECoG where skull removal Under recording/stimulation surgery is required. 3) higher feasibility of freely movement of patient under study − compared to both EEG and ECoG methods where lots of wires are connected to the patient under operation. 4) long-term usage as the implantable interface is wireless − compared to both EEG and ECoG methods where it is practical for only a limited time under operation. We present the architecture of a wireless network of implantable microsystems, which we call it Brain Area Sensor NETwork (Brain-ASNET). There are two main challenges in realization of the proposed Brain-ASNET. 1) design and implementation of power-hungry RF transceiver of the implantable network sensors' chip, and, 2) design of an energy-efficient ad-hoc Wireless Sensor Network (WSN) protocol. In this thesis, we introduce an energy-efficient ad-hoc network protocol for the desired network, along with a method to overcome the issue of variable packet length caused by bit stuffing process in standard HDLC protocol. The proposed ad-hoc protocol designed for Brain-ASNET shows better energy-efficiency compared to standard protocols like ZigBee, Bluetooth, and Wi-Fi as well as state-of-the-art ad-hoc protocols. The protocol was designed and tested by MATLAB and Simulink

Doctor of Philosophy

dissertationSince the late 1950s, scientists have been working toward realizing implantable devices that would directly monitor or even control the human body's internal activities. Sophisticated microsystems are used to improve our understanding of internal biological processes in animals and humans. The diversity of biomedical research dictates that microsystems must be developed and customized specifically for each new application. For advanced long-term experiments, a custom designed system-on-chip (SoC) is usually necessary to meet desired specifications. Custom SoCs, however, are often prohibitively expensive, preventing many new ideas from being explored. In this work, we have identified a set of sensors that are frequently used in biomedical research and developed a single-chip integrated microsystem that offers the most commonly used sensor interfaces, high computational power, and which requires minimum external components to operate. Included peripherals can also drive chemical reactions by setting the appropriate voltages or currents across electrodes. The SoC is highly modular and well suited for prototyping in and ex vivo experimental devices. The system runs from a primary or secondary battery that can be recharged via two inductively coupled coils. The SoC includes a 16-bit microprocessor with 32 kB of on chip SRAM. The digital core consumes 350 μW at 10 MHz and is capable of running at frequencies up to 200 MHz. The integrated microsystem has been fabricated in a 65 nm CMOS technology and the silicon has been fully tested. Integrated peripherals include two sigma-delta analog-to-digital converters, two 10-bit digital-to-analog converters, and a sleep mode timer. The system also includes a wireless ultra-wideband (UWB) transmitter. The fullydigital transmitter implementation occupies 68 x 68 μm2 of silicon area, consumes 0.72 μW static power, and achieves an energy efficiency of 19 pJ/pulse at 200 MHz pulse repetition frequency. An investigation of the suitability of the UWB technology for neural recording systems is also presented. Experimental data capturing the UWB signal transmission through an animal head are presented and a statistical model for large-scale signal fading is developed

Towards Next Generation Neural Interfaces: Optimizing Power, Bandwidth and Data Quality

In this paper, we review the state-of-the-art in neural interface recording architectures. Through this we identify schemes which show the trade-off between data information quality (lossiness), computation (i.e. power and area requirements) and the number of channels. These trade-offs are then extended by considering the front-end amplifier bandwidth to also be a variable. We therefore explore the possibility of band-limiting the spectral content of recorded neural signals (to save power) and investigate the effect this has on subsequent processing (spike detection accuracy). We identify the spike detection method most robust to such signals, optimize the threshold levels and modify this to exploit such a strategy.Accepted versio

Calibration-free and hardware-efficient neural spike detection for brain machine interfaces

Recent translational efforts in brain-machine interfaces (BMI) are demonstrating the potential to help people with neurological disorders. The current trend in BMI technology is to increase the number of recording channels to the thousands, resulting in the generation of vast amounts of raw data. This in turn places high bandwidth requirements for data transmission, which increases power consumption and thermal dissipation of implanted systems. On-implant compression and/or feature extraction are therefore becoming essential to limiting this increase in bandwidth, but add further power constraints – the power required for data reduction must remain less than the power saved through bandwidth reduction. Spike detection is a common feature extraction technique used for intracortical BMIs. In this paper, we develop a novel firing-rate-based spike detection algorithm that requires no external training and is hardware efficient and therefore ideally suited for real-time applications. Key performance and implementation metrics such as detection accuracy, adaptability in chronic deployment, power consumption, area utilization, and channel scalability are benchmarked against existing methods using various datasets. The algorithm is first validated using a reconfigurable hardware (FPGA) platform and then ported to a digital ASIC implementation in both 65 nm and 0.18MU m CMOS technologies. The 128-channel ASIC design implemented in a 65 nm CMOS technology occupies 0.096 mm2 silicon area and consumes 4.86MU W from a 1.2 V power supply. The adaptive algorithm achieves a 96% spike detection accuracy on a commonly used synthetic dataset, without the need for any prior training

Neuromorphic hardware for somatosensory neuroprostheses

In individuals with sensory-motor impairments, missing limb functions can be restored using neuroprosthetic devices that directly interface with the nervous system. However, restoring the natural tactile experience through electrical neural stimulation requires complex encoding strategies. Indeed, they are presently limited in effectively conveying or restoring tactile sensations by bandwidth constraints. Neuromorphic technology, which mimics the natural behavior of neurons and synapses, holds promise for replicating the encoding of natural touch, potentially informing neurostimulation design. In this perspective, we propose that incorporating neuromorphic technologies into neuroprostheses could be an effective approach for developing more natural human-machine interfaces, potentially leading to advancements in device performance, acceptability, and embeddability. We also highlight ongoing challenges and the required actions to facilitate the future integration of these advanced technologies

Wireless Neurosensor for Full-Spectrum Electrophysiology Recordings during Free Behavior

SummaryBrain recordings in large animal models and humans typically rely on a tethered connection, which has restricted the spectrum of accessible experimental and clinical applications. To overcome this limitation, we have engineered a compact, lightweight, high data rate wireless neurosensor capable of recording the full spectrum of electrophysiological signals from the cortex of mobile subjects. The wireless communication system exploits a spatially distributed network of synchronized receivers that is scalable to hundreds of channels and vast environments. To demonstrate the versatility of our wireless neurosensor, we monitored cortical neuron populations in freely behaving nonhuman primates during natural locomotion and sleep-wake transitions in ecologically equivalent settings. The interface is electrically safe and compatible with the majority of existing neural probes, which may support previously inaccessible experimental and clinical research

Neuromorphic Neuromodulation: Towards the next generation of on-device AI-revolution in electroceuticals

Neuromodulation techniques have emerged as promising approaches for treating a wide range of neurological disorders, precisely delivering electrical stimulation to modulate abnormal neuronal activity. While leveraging the unique capabilities of artificial intelligence (AI) holds immense potential for responsive neurostimulation, it appears as an extremely challenging proposition where real-time (low-latency) processing, low power consumption, and heat constraints are limiting factors. The use of sophisticated AI-driven models for personalized neurostimulation depends on back-telemetry of data to external systems (e.g. cloud-based medical mesosystems and ecosystems). While this can be a solution, integrating continuous learning within implantable neuromodulation devices for several applications, such as seizure prediction in epilepsy, is an open question. We believe neuromorphic architectures hold an outstanding potential to open new avenues for sophisticated on-chip analysis of neural signals and AI-driven personalized treatments. With more than three orders of magnitude reduction in the total data required for data processing and feature extraction, the high power- and memory-efficiency of neuromorphic computing to hardware-firmware co-design can be considered as the solution-in-the-making to resource-constraint implantable neuromodulation systems. This could lead to a new breed of closed-loop responsive and personalised feedback, which we describe as Neuromorphic Neuromodulation. This can empower precise and adaptive modulation strategies by integrating neuromorphic AI as tightly as possible to the site of the sensors and stimulators. This paper presents a perspective on the potential of Neuromorphic Neuromodulation, emphasizing its capacity to revolutionize implantable brain-machine microsystems and significantly improve patient-specificity.Comment: 17 page

Hardware-efficient compression of neural multi-unit activity

Brain-machine interfaces (BMI) are tools for measuring neural activity in the brain, used to treat numerous conditions. It is essential that the next generation of intracortical BMIs is wireless so as to remove percutaneous connections, i.e. wires, and the associated mechanical and infection risks. This is required for the effective translation of BMIs into clinical applications and is one of the remaining bottlenecks. However, due to cortical tissue thermal dissipation safety limits, the on-implant power consumption must be strictly limited. Therefore, both the neural signal processing and wireless communication power should be minimal, while the implants should provide signals that offer high behavioural decoding performance (BDP). The Multi-Unit Activity (MUA) signal is the most common signal in modern BMIs. However, with an ever-increasing channel count, the raw data bandwidth is becoming prohibitively high due to the associated communication power exceeding the safety limits. Data compression is therefore required. To meet this need, this work developed hardware-efficient static Huffman compression schemes for MUA data. Our final system reduced the bandwidth to 27 bps/channel, compared to the standard MUA rate of 1 kbps/channel. This compression is over an order of magnitude more than has been achieved before, while using only 0.96 uW/channel processing power and 246 logic cells. Our results were verified on 3 datasets and less than 1% loss in BDP was observed. As such, with the use of effective data compression, an order more of MUA channels can be fitted on-implant, enabling the next generation of high-performance wireless intracortical BMIs