25,533 research outputs found

    Spin-Based Neuron Model with Domain Wall Magnets as Synapse

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    We present artificial neural network design using spin devices that achieves ultra low voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nano-magnets for modelling neuron and domain wall magnets for compact, programmable synapses. The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power. CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices. Simulation results for character recognition as a benchmark application shows 95% lower power consumption as compared to 45nm CMOS design

    An Ultra-Low-Voltage and Ultra-Low-Power 2.4 GHz LNA Design

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    In this paper, ultra-low-voltage and ultra-low-power circuit techniques are presented for CMOS RF front-ends. By employing a modified current-reused architecture, the low-noise amplifier (LNA) can operate at a very low supply voltage with microwatt power consumption while maintaining reasonable circuit performance at 2.4 GHz. Using a TSMC 0.18 um CMOS process, from the simulation results, the fully integrated LNA exhibits a gain of 14.4 dB and a noise figure of 1.6 dB at 2.4 GHz, operated at a supply voltage of 0.9 V, the input matching (S11) is –18.1 dB while consumes only 960 μW. example

    Design of ultra-low voltage 0.5V CMOS current bleeding mixer

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    This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4GHz frequency band. It introduces and discusses a modified CMOS based current bleeding mixer topology adopting a combination of NMOS current bleeding transistor, with a PMOS Local Oscillator (LO) switching stage and integrated inductors to achieve ultra-low voltage headroom operation at 0.5V. This mixer is simulated and verified in 0.13µm standard CMOS technology. The result shows a conversion gain (CG) of 11.84dB, 1dB compression point (P1dB) at -14.36dBm, third-order intercept point (IIP3) of -5dBm and a noise figure (NF) of 15dB and with a power consumption of 930µW

    Ultra-low Voltage CMOS Cascode Amplifier

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    Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

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    The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

    Design of Ultra Low Power Integrated PLL using Ring VCO

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    The design of an ultra low power Phase Locked Loop (PLL) is presented in this paper. The proposed PLL consists of a phase detector, a charge pump, low pass filter, and a ring oscillator based voltage controlled oscillator (VCO). The performance of Voltage Controlled Oscillator is of great importance for PLL. The circuit is designed using 0.13µm CMOS technology with the supply voltage of 1V and has a power consumption of 254µW. Keywords: Charge Pump, CMOS Technology, Low Pass Filter, Phase Detector, Phase Locked Loop, Voltage Controlled Oscillator
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