24,037 research outputs found

    Spin-Based Neuron Model with Domain Wall Magnets as Synapse

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    We present artificial neural network design using spin devices that achieves ultra low voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nano-magnets for modelling neuron and domain wall magnets for compact, programmable synapses. The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power. CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices. Simulation results for character recognition as a benchmark application shows 95% lower power consumption as compared to 45nm CMOS design

    Analog Circuits in Ultra-Deep-Submicron CMOS

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    Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena

    A Fully Differential Digital CMOS Pulse UWB Generator

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    A new fully-digital CMOS pulse generator for impulse-radio Ultra-Wide-Band (UWB) systems is presented. First, the shape of the pulse which best fits the FCC regulation in the 3.1-5 GHz sub-band of the entire 3.1-10.6 GHz UWB bandwidth is derived and approximated using rectangular digital pulses. In particular, the number and width of pulses that approximate an ideal template is found through an ad-hoc optimization methodology. Then a fully differential digital CMOS circuit that synthesizes the pulse sequence is conceived and its functionality demonstrated through post-layout simulations. The results show a very good agreement with the FCC requirements and a low power consumptio

    Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

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    CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

    Low-power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator

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    We present a novel driver circuit enabling electro-optic modulation with high extinction ratio from a co-designed silicon ring modulator. The driver circuit provides an asymmetric differential output at 10Gbps with a voltage swing up to 1.5V(pp) from a single 1.0V supply, maximizing the resonance-wavelength shift of depletion-type ring modulators while avoiding carrier injection. A test chip containing 4 reconfigurable driver circuits was fabricated in 40nm CMOS technology. The measured energy consumption for driving a 100fF capacitive load at 10Gbps was as low as 125fJ/bit and 220fJ/bit at 1V(pp) and 1.5V(pp) respectively. After flip-chip integration with ring modulators on a silicon-photonics chip, the power consumption was measured to be 210fJ/bit and 350fJ/bit respectively
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