176 research outputs found

    On Statistical QoS Provisioning for Smart Grid

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    Current power system is in the transition from traditional power grid to Smart Grid. A key advantage of Smart Grid is its integration of advanced communication technologies, which can provide real-time system-wide two-way information links. Since the communication system and power system are deeply coupled within the Smart Grid system, it makes Quality of Service (QoS) performance analysis much more complex than that in either system alone. In order to address this challenge, the effective rate theory is studied and extended in this thesis, where a new H transform based framework is proposed. Various scenarios are investigated using the new proposed effective rate framework, including both independent and correlated fading channels. With the effective rate as a connection between the communication system and the power system, an analysis of the power grid observability under communication constraints is performed. Case studies show that the effective rate provides a cross layer analytical framework within the communication system, while its statistical characterisation of the communication delay has the potential to be applied as a general coupling point between the communication system and the power system, especially when real-time applications are considered. Besides the theoretical QoS performance analysis within Smart Grid, a new Software Defined Smart Grid testbed is proposed in this thesis. This testbed provides a versatile evaluation and development environment for Smart Grid QoS performance studies. It exploits the Real Time Digital Simulator (RTDS) to emulate different power grid configurations and the Software Defined Radio (SDR) environment to implement the communication system. A data acquisition and actuator module is developed, which provides an emulation of various Intelligent Electronic Devices (IEDs). The implemented prototype demonstrates that the proposed testbed has the potential to evaluate real time Smart Grid applications such as real time voltage stability control

    Contribution to the Federation of the asynchronous SmartSantander service layer within the European Fed4FIRE context

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    This thesis is a contribution to the federation of asynchronous SmartSantander service layer within the European Fed4FIRE context. The thesis was developed in a Smart City background, and its main aims were both to gain knowledge of how Smart Cities, Testbeds and Federations of Testbeds are structured by working on a real deployed system, i.e. SmartSantander framework and Fed4FIRE federation, and to contribute with some of the components required for the integratio

    Proceedings of the ACM SIGIR Workshop ''Searching Spontaneous Conversational Speech''

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    Quality of service schemes for mobile ad-hoc networks

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    To achieve QoS, independently of the routing protocol, each mobile node participating in the network must implement traffic conditioning, traffic marking and buffer management (Random Early Drop with in- out dropping) or queue scheduling (Priority Queuing) schemes. In MANETs, since the mobile nodes can have simultaneous multiple roles (ingress, interior and destination), it was found that traffic conditioning and marking must be implemented in all mobile nodes acting as source (ingress) nodes. Buffer management and queue scheduling schemes must be performed by all mobile nodes. By utilizing the Network Simulator (NS2) tool, this thesis focused on the empirical performance evaluation of the QoS schemes for different types of traffic (FTP/TCP, CBR/UDP and VBRI/UDP, geographical areas of different sizes and various mobility levels. Key metrics, such as throughput, end-to-end delay and packet loss rates, were used to measure the relative improvements of QoS- enabled traffic sessions. The results indicate that in the presence of congestion, service differentiation can be achieved under different scenarios and for different types of traffic, whenever a physical connection between two nodes is realizable.http://archive.org/details/qualityofservice109451082

    Journal of Telecommunications and Information Technology, 2008, nr 2

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    Embedded electronic systems driven by run-time reconfigurable hardware

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    Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria
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