The STAR MAPS-based PiXeL detector

The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014-2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this paper

Design of an FPGA Based High-Speed Data Acquisition System for Frequency Scanning Interferometry Long Range Measurement

Frequency Scanning Interferometry (FSI) has become a popular method for long-range, target based, distance measurements. However, the cost of developing such systems, particularly the electronic components required for high-speed data acquisition, remains a significant concern. In this paper, we present a cost-effective, FPGA-based real-time data acquisition system specifically designed for FSI, with a focus on long absolute distance measurements. Our design minimizes the use of third-party intellectual property (IP) and is fully compatible with the Xilinx FPGA 7 series families. The hardware employs a 160 MS/s, 16-bit dual-channel ADC interfaced to the FPGA via a Low Voltage Differential Signal (LVDS). The proposed system incorporates an external sampling clock, referred to as the K- clock, which linearizes the laser's tuning rate, enabling optical measurements to be sampled at equal optical frequency intervals rather than equal time intervals. Additionally, we present the design of a high-speed, 160 MS/s ADC module for the front-end analogue signal interface and the LVDS connection to the chosen FPGA. We demonstrate that the digitized data samples can be efficiently transmitted to a PC application via a USB interface for further processing

Development of an enhanced transfer data channel for a hybrid SoC FPGA used in a DAQ system aimed at improving hadrontherapy protocols

In questa tesi è presentato il lavoro svolto su un sistema di acquisizione utilizzato in un esperimento di fisica nucleare facente parte del progetto FOOT, volto ad ottenere ulteriori informazioni sulla frammentazione nucleare per migliorare i protocolli medici di adroterapia e le metodologie di radioprotezione spaziale. Il sistema si basa su una scheda Terasic DE10-Nano che monta un SoC FPGA Cyclone V. L'obiettivo principale del lavoro è stato aumentare il throughput del trasferimento dei dati acquisiti dai sensori verso la memoria principale: a tal fine è stata utilizzata direttamente la memoria RAM del processore integrato come buffer circolare temporaneo. È stata inoltre implementata l'interfaccia (realizzata dall'Università di Perugia) per la sensoristica e un controller per l'ADC della scheda. Il lavoro ha compreso sia lo sviluppo del firmware, quindi VHDL e Platform Designer, sia del software, con la scrittura di funzioni in C++ per l'interfacciamento all'hardware. È stata inoltre necessaria una modifica al Device Tree del kernel del sistema operativo Linux presente sul SoC. Il sistema è stato simulato e testato in laboratorio con esito positivo. La scheda DE10-Nano vanta un banda di trasmissione massima teorica di 60 MB/s, che però scende a circa 10 MB/s quando la scheda è installata nel sistema completo di acquisizione, limitazione dovuta a fattori esterni alla scheda, come lo stato della rete del laboratorio e l'overhead degli altri componenti. Questi risultati sono eccellenti e, inoltre, il massimo throughput di 60 MB/s supporterà future ottimizzazioni del sistema senza creare colli di bottiglia per gli altri dispositivi. Operazioni di ottimizzazione sull'infrastruttura sono tutt'ora in corso, quindi ci si aspetta un ulteriore incremento della performance in un vicino futuro

Conception d'un injecteur de données hardware

L'expérience LHCb, menée dans le cadre du CERN, recueille un nombre extraordinaire de données. Le système d'acquisition de ces données est donc démesuré, entièrement dédié à cette tâche. Pour réaliser des tests sur ce système d'acquisition, hors expérience, il existe un injecteur de données qui permet de simuler le flot habituel. Dans l'optique d'une future optimisation du réseau de ce système en Ethernet 10 gigabit, le LHCb souhaite se doter d'un injecteur hardware permettant de fonctionner sur ce nouveau réseau et d'y tester différents types de protocoles de communication tels qu'IP, MEP et TCP. Cet injecteur est réalisé au moyen d'une carte de développement Altera munie d'un FPGA et de différentes interfaces de communications

Firmware Development and Integration for ALICE TPC and PHOS Front-end Electronics: A Trigger Based Readout and Control System operating in a Radiation Environment

The readout electronics in PHOS and TPC - two of the major detectors of the ALICE experiment at the LHC - consist of a set of Front End Cards (FECs) that digitize, process and buffer the data from the detector sensors. The FECs are connected to a Readout Control Unit (RCU) via two sets of custom made PCB backplanes. For PHOS, 28 FECs are connected to one RCU, while for TPC the number is varying from 18 to 25 FECs depending on location. The RCU is in charge of the data readout, including reception and distribution of triggers and in moving the data from the FECs to the Data Acquisition System. In addition it does low level control tasks. The RCU consists of an RCU Motherboard that hosts a Detector Control System (DCS) board and a Source Interface Unit. The DCS board is an embedded computer running Linux that controls the readout electronics. All the mentioned devices are implemented in commercial grade SRAM based Field Programmable Gate Arrays (FPGAs). Even if these devices are not very radiation tolerant, they are chosen because of their cost and flexibility, and most importantly the possibility to easily do future upgrades of the electronics. Since physical shielding of the electronics is not possible in ALICE due to the architecture of the detector, the radiation related errors need to be handled with other techniques such as firmware mitigation techniques. The main objective of this thesis has been to make firmware modules for the FPGAs reciding in different parts of the readout electronics. Because of the flexibility of the designs, some of them have, with minor adaptations, been applied in different devices surrounding the readout electronics. Additionally, effort has been put into testing and integration of the system. In detail, the work presented in this thesis can be summarized as follows: - Firmware design for radiation environments. All firmware modules that are designed are to be used in a radiation environment, and then special precautions need to be taken. Additionally, a state-of-the-art solution has been designed for protecting the main FPGA on the RCU Motherboard against radiation induced functional failures. - Implementation of Trigger Handling for the TPC/PHOS Readout Electronics. The triggers are received from the global trigger system via an optical link and are handled by an Application Spesific Integrated Circuit (ASIC) on the DCS board. The problem is that the DCS board might have occasional down time 6 due to radiation related errors, so a special interface module is designed for the main FPGA on the RCU Motherboard. This module decodes and verifies the information received from the trigger system. As it is a generic design it has also been implemented as part of the BusyBox. The BusyBox is an important device in the trigger path of the TPC and PHOS sub-detectors. - Testing and Verification of all firmware modules. All firmware modules have been extensively verified with computer simulation before being tested in real hardware. - Maintenance of the DCS board for TPC/PHOS and of the different Fee firmware modules in general. - System Integration and System Level Tests. A big contribution has been done integrating and testing all the modules and sub-systems. This concern both locally on the RCU and the BusyBox, as well as making all the devices play together on a larger scale. - Testing and Verification of all firmware modules. All firmware modules have been extensively verified with computer simulation before being tested in real hardware. - Maintenance of the DCS board for TPC/PHOS and of the different Fee firmware modules in general. - System Integration and System Level Tests. A big contribution has been done integrating and testing all the modules and sub-systems. This concern both locally on the RCU and the BusyBox, as well as making all the devices play together on a larger scale. As the presented electronics are located in a radiation environment and are physically unavailable after commissioning, effort has been put into making designs that are reliable, scalable and possible to upgrade. This has been ensured by following a systematic design approach where testability, version management and documentation are key elements. Some parts of the work described in this thesis have been published and presented in international peer reviewed publications and conferences