119 research outputs found
Partial Reconfiguration in the Field of Logic Controllers Design
The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process
Hybrid Linux System Modeling with Mixed-Level Simulation
Dissertação de mestrado integrado em Engenharia Electrónica Industrial e ComputadoresWe live in a world where the need for computer-based systems with better performances
is growing fast, and part of these systems are embedded systems. This
kind of systems are everywhere around us, and we use them everyday even without
noticing. Nevertheless, there are issues related to embedded systems in what comes
to real-time requirements, because the failure of such systems can be harmful
to the user or its environment.
For this reason, a common technique to meet real-time requirements in difficult
scenarios is accelerating software applications by using parallelization techniques
and dedicated hardware components. This dissertations’ goal is to adopt a methodology
of hardware-software co-design aided by co-simulation, making the design
flow more efficient and reliable. An isolated validation does not guarantee integral
system functionality, but the use of an integrated co-simulation environment
allows detecting system problems before moving to the physical implementation.
In this dissertation, an integrated co-simulation environment will be developed,
using the Quick EMUlator (QEMU) as a tool for emulating embedded software
platforms in a Linux-based environment. A SystemVerilog Direct Programming
Interface (DPI) Library was developed in order to allow SystemVerilog simulators
that support DPI to perform co-simulation with QEMU. A library for DLL
blocks was also developed in order to allow PSIMR to communicate with QEMU.
Together with QEMU, these libraries open up the possibility to co-simulate several
parts of a system that includes power electronics and hardware acceleration
together with an emulated embedded platform.
In order to validate the functionality of the developed co-simulation environment,
a demonstration application scenario was developed following a design flow that
takes advantage of the mentioned simulation environment capabilities.Vivemos num mundo em que a procura por sistemas computer-based com desempenhos
cada vez melhores domina o mercado. Estamos rodeados por este tipo de
sistemas, usando-os todos os dias sem nos apercebermos disso, sendo grande parte
deles sistemas embebidos. Ainda assim, existem problemas relacionados com os
sistemas embebidos no que toca aos requisitos de tempo-real, porque uma falha
destes sistemas pode ser perigosa para o utilizador ou o ambiente que o rodeia.
Devido a isto, uma técnica comum para se conseguir cumprir os requisitos de
tempo-real em aplicações críticas é a aceleração de aplicações de software, utilizando
técnicas de paralelização e o uso de componentes de hardware dedicados.
O objetivo desta dissertação é adotar uma metodologia de co-design de hardwaresoftware
apoiada em co-simulação, tornando o design flow mais eficiente e fiável.
Uma validação isolada não garante a funcionalidade do sistema completo, mas a
utilização de um ambiente de co-simulação permite detetar problemas no sistema
antes deste ser implementado na plataforma alvo.
Nesta dissertação será desenvolvido um ambiente de co-simulação usando o QEMU
como emulador para as plataformas de software "embebido" baseadas em Linux.
Uma biblioteca para SystemVerilog DPI foi desenvolvida, que permite a co-simulação
entre o QEMU e simuladores de Register-Transfer Level (RTL) que suportem SystemVerilog.
Foi também desenvolvida uma biblioteca para os blocos Dynamic Link
Library (DLL) do PSIMR , de modo a permitir a ligação ao QEMU. Em conjunto,
as bibliotecas desenvolvidas permitem a co-simulação de diversas partes do sistema,
nomeadamente do hardware de eletrónica de potência e dos aceleradores de
hardware, juntamente com a plataforma embebida emulada no QEMU.Para validar as funcionalidades do ambiente de co-simulação desenvolvido, foi explorado
um cenário de aplicação que tem por base esse mesmo ambiente
Hardware Certification for Real-time Safety-critical Systems: State of the Art
This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification. In particular, problems related to circuits’ compliance with DO-254 in avionics and other industries are considered. Extensive literature review of the subject is given, including current views on and experiences of chip manufacturers and EDA industry with qualification of hardware design tools, including formal approaches to hardware verification. Some results of the authors’ own study on tool qualification are presented
Portable Waveform Development for Software Defined Radios
This work focuses on the question: "How can we build waveforms that can be moved from one platform to another?\u27\u27 Therefore an approach based on the Model Driven Architecture was evaluated. Furthermore, a proof of concept is given with the port of a TETRA waveform from a USRP platform to an SFF SDR platform
Methoden und Beschreibungssprachen zur Modellierung und Verifikation vonSchaltungen und Systemen: MBMV 2015 - Tagungsband, Chemnitz, 03. - 04. März 2015
Der Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015) findet nun schon zum 18. mal statt. Ausrichter sind in diesem Jahr die Professur Schaltkreis- und Systementwurf der Technischen Universität Chemnitz und das Steinbeis-Forschungszentrum Systementwurf und Test.
Der Workshop hat es sich zum Ziel gesetzt, neueste Trends, Ergebnisse und aktuelle Probleme auf dem Gebiet der Methoden zur Modellierung und Verifikation sowie der Beschreibungssprachen digitaler, analoger und Mixed-Signal-Schaltungen zu diskutieren. Er soll somit ein Forum zum Ideenaustausch sein.
Weiterhin bietet der Workshop eine Plattform für den Austausch zwischen Forschung und Industrie sowie zur Pflege bestehender und zur Knüpfung neuer Kontakte. Jungen Wissenschaftlern erlaubt er, ihre Ideen und Ansätze einem breiten Publikum aus Wissenschaft und Wirtschaft zu präsentieren und im Rahmen der Veranstaltung auch fundiert zu diskutieren. Sein langjähriges Bestehen hat ihn zu einer festen Größe in vielen Veranstaltungskalendern gemacht. Traditionell sind auch die Treffen der ITGFachgruppen an den Workshop angegliedert.
In diesem Jahr nutzen zwei im Rahmen der InnoProfile-Transfer-Initiative durch das Bundesministerium für Bildung und Forschung geförderte Projekte den Workshop, um in zwei eigenen Tracks ihre Forschungsergebnisse einem breiten Publikum zu präsentieren. Vertreter der Projekte Generische Plattform für Systemzuverlässigkeit und Verifikation (GPZV) und GINKO - Generische Infrastruktur zur nahtlosen energetischen Kopplung von Elektrofahrzeugen stellen Teile ihrer gegenwärtigen Arbeiten vor. Dies bereichert denWorkshop durch zusätzliche Themenschwerpunkte und bietet eine wertvolle Ergänzung zu den Beiträgen der Autoren. [... aus dem Vorwort
Reconfigurable Computing Systems for Robotics using a Component-Oriented Approach
Robotic platforms are becoming more complex due to the wide range of modern applications, including multiple heterogeneous sensors and actuators. In order to comply with real-time and power-consumption constraints, these systems need to process a large amount of heterogeneous data from multiple sensors and take action (via actuators), which represents a problem as the resources of these systems have limitations in memory storage, bandwidth, and computational power.
Field Programmable Gate Arrays (FPGAs) are programmable logic devices that offer high-speed parallel processing. FPGAs are particularly well-suited for applications that require real-time processing, high bandwidth, and low latency. One of the fundamental advantages of FPGAs is their flexibility in designing hardware tailored to specific needs, making them adaptable to a wide range of applications. They can be programmed to pre-process data close to sensors, which reduces the amount of data that needs to be transferred to other computing resources, improving overall system efficiency. Additionally, the reprogrammability of FPGAs enables them to be repurposed for different applications, providing a cost-effective solution that needs to adapt quickly to changing demands. FPGAs' performance per watt is close to that of Application-Specific Integrated Circuits (ASICs), with the added advantage of being reprogrammable.
Despite all the advantages of FPGAs (e.g., energy efficiency, computing capabilities), the robotics community has not fully included them so far as part of their systems for several reasons. First, designing FPGA-based solutions requires hardware knowledge and longer development times as their programmability is more challenging than Central Processing Units (CPUs) or Graphics Processing Units (GPUs). Second, porting a robotics application (or parts of it) from software to an accelerator requires adequate interfaces between software and FPGAs. Third, the robotics workflow is already complex on its own, combining several fields such as mechanics, electronics, and software.
There have been partial contributions in the state-of-the-art for FPGAs as part of robotics systems. However, a study of FPGAs as a whole for robotics systems is missing in the literature, which is the primary goal of this dissertation. Three main objectives have been established to accomplish this. (1) Define all components required for an FPGAs-based system for robotics applications as a whole. (2) Establish how all the defined components are related. (3) With the help of Model-Driven Engineering (MDE) techniques, generate these components, deploy them, and integrate them into existing solutions.
The component-oriented approach proposed in this dissertation provides a proper solution for designing and implementing FPGA-based designs for robotics applications.
The modular architecture, the tool 'FPGA Interfaces for Robotics Middlewares' (FIRM), and the toolchain 'FPGA Architectures for Robotics' (FAR) provide a set of tools and a comprehensive design process that enables the development of complex FPGA-based designs more straightforwardly and efficiently. The component-oriented approach contributed to the state-of-the-art in FPGA-based designs significantly for robotics applications and helps to promote their wider adoption and use by specialists with little FPGA knowledge
Timing Architecture for ESS
Programa Oficial de Doutoramento en Investigación en Tecnoloxías da Información. 5023V01[Resumo]
O sistema de temporización é unha compoñente fundamental para o control e sincronización de
instalacións industriais e científicas, coma aceleradores de partículas. Nesta tese
traballamos na especificación e desenvolvemento do sistema de temporización para a European
Spallation Source (ESS), a maior fonte de neutróns actualmente en construción. Abordamos
este tra ballo a dous niveis: a especificación do sistema de temporización, e a imple mentación
física de sistemas de control empregando circuítos reconfigurables.
Con respecto á especificación do sistema de temporización, deseñamos e implementamos a
configuración do protocolo de temporización para cumprir cos requirimentos do ESS e ideamos un modo
de operación e unha aplicación para a configuración e control do sistema de temporización.
Tamén presentamos unha ferramenta e unha metodoloxía para imple mentar sistemas de
control empregando FPGAs, coma os nodos do sistema de temporización. ámbalas <lúas están baseadas
en statecharts, unha repre sentación gráfica de sistemas que expande o concepto de máquinas de
estados finitos, orientada a sistemas que necesitan ser reconfigurados rápidamente en múltiples
localizacións minimizando a posibilidade de erros. A ferramenta crea automaticamente código
VHDL sintetizable a partir do statechart do sistema. A metodoloxía explica o procedemento
para implementar o state chart como unha arquitectura microprogramada en FPGAs.[Resumen]
El sistema de temporización es un componente fundamental para el control y sincronización de
instalaciones industriales y científicas, como aceleradores e partículas. En esta tesis
trabajamos en la especificación y desarrollo el sistema de temporización para la European
Spallation Source (ESS), la mayor fuente de neutrones actualmente en construcción.
Abordamos este trabajo en dos niveles: la especificación del sistema de temporización, y la
mplementación física de sistemas de control empleando circuitos reconfig rables.
Con respecto a la especificación del sistema de temporización, diseñamos
e implementamos la configuración del protocolo de temporización para cumplir on los requisitos de
ESS e ideamos un modo de operación y una aplicación ara la configuración y control del sistema
de temporización.
También presentamos una herramienta y una metodología para imple entar sistemas de control
empleando FPGAs, como los nodos del sistema e temporización. Ambas están basadas en statecharts)
una representación gráfica de sistemas que expande el concepto de máquinas de estados
fini os, orientada a sistemas que necesitan ser reconfigurados rápidamente en últiples
localizaciones minimizando la posibilidad de errores. La herramienta crea
automáticamente código VHDL sintetizable a partir del statechart del sistema. La metodología
explica el procedimiento para implementar el statechart como una arquitectura microprogramada en FPGAs.[Abstract]
The timing system is a key component for the control and synchronization of industrial and
scientific facilities, such as particle accelerators. In this thesis we tackle the
specification and development of the timing system for the European Spallation Source (ESS), the
largest neutron source currently in construction. We approach this work at two levels:
the specification of the timing system and the physical implementation of control systems using
reconfigurable hardware.
Regarding the specification of the timing system, we designed and imple mented the configuration
of the timing protocol to fulfil the requirements of ESS and devised an operation mode andan
application for the configuration and control of the timing system.
We also present one too! and one methodology to implement control systems using FPGAs,
such as the nodes of the timing system. Both are based on statecharts, a graphical
representation of systems that expand the concepts of Finite State Machines, targeted at
systems that need to be re configured quickly in multiple locations minimizing the
chance of errors. The too! automatically creates synthesizable VHDL code from a statechart of
the system. The methodology explains the procedure to implement the statechart as a
microprogrammed architecture in FPGAs
FPGA based Embedded System to control an electric vehicle and the driver assistance systems
This Master Thesis involves the development of an embedded system based on FPGA
for controlling an electric vehicle based on a Kart platform and its electronic driving
aids. It consists of two distinct stages in the process of hardware-software co-design,
hardware development, which includes all the elements of the periphery of the processor
and communication elements, all developed in VHDL. An important part of the hardware
development also include the development of electronic driving aids, which include traction
control and torque vectoring differential gear, in hardware coprocessors, also writen in
VHDL. The other part of the co-design is the development of the control software, which
is going to be executed by the embedded system’s processor. This Master Thesis will be
used in a range of new electric vehicles that will be built in a near future and also gives
the base for future thesis in the fields of automotive, electronics and computing
UML-Based co-design framework for body sensor network applications
Ph.DDOCTOR OF PHILOSOPH
Characterizing Single Event Upsets within the lpGBT-based End-of-Substructure Card
The CERN ATLAS particle physics experiment is currently undergoing a significant system upgrade (ATLAS Phase II upgrade). As a result of the upgrade the experiment's Inner Tracker (ITk) and the front-end electronics of the ITk are being redesigned to handle increased data rates and a higher radiation environment. Within the ITk, the End Of Substructure (EoS) card is a new custom designed digital board that will provide the data, command, and power interface between on and off-detector electronics. Each EoS card makes use of one or two custom CERN designed low power Gigabit Transceivers (lpGBTs) ASICS that have been created for the purposes of supporting high bandwidth optical links in high radiation environments throughout CERN experiments. An estimated 1552 EoS cards will be installed in the ITk, each representing a potential point of failure. Given the complexity and quantity of new hardware designs involved, and that the EoS cards will be not be accessible or serviceable after the upgrade has been completed, there is a need for rigorous quality assurance (QA) and quality control (QC) testing. This thesis therefore describes an independent test setup commissioned, by the author, at the University of Cape Town (UCT) Physics Department for characterising aspects of EoS card's operation under representative radiation conditions. Specifically, the radiation environment of the ITk poses a challenge to electronics as energetic particles can deposit their energy within the circuit material resulting in an erroneous change in logic known as a Single Event Upset (SEU). The lpGBT is a radiation tolerant ASIC and employs digital signal processing (DSP) and triple modular redundancy (TMR) techniques to mitigate against the effects of SEUs on transmitted data. This thesis presents an experiment setup which tests this hypothesis that the DSP stages are susceptible to data corruption caused by SEUs. In addition the setup also attempts to characterize the susceptibility of the scrambler, encoder, and interleaver stages within the lpGBT to SEUs. This experiment is carried out by actively irradiating an EoS card with a neutron source (energy spectrum of up to 11 MeV), while emulating each stage on a non-irradiated off-board FPGA. Additionally and in support of this experiment, the existing firmware and LabView automation software developed at DESY are extended. Results from this thesis indicate that the DSP stages within the lpGBT are susceptible to data corruption caused by SEUs. It was also shown that the susceptibility of the experiment itself did not effect the measured SEU rates. Finally, preliminary results suggest that susceptibility of the DSP stages within the lpGBT can be characterized as the Bit Error Rate (BER) increases depending on the number of active stages
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