Design and implementation of an electro-optical backplane with pluggable in-plane connectors

The design, implementation and characterisation of an electro-optical backplane and an active pluggable in-plane optical connector technology is presented. The connection architecture adopted allows line cards to be mated to and unmated from a passive electro-optical backplane with embedded polymeric waveguides. The active connectors incorporate a photonics interface operating at 850 nm and a mechanism to passively align the interface to the optical waveguides embedded in the backplane. A demonstration platform has been constructed to assess the viability of embedded electro-optical backplane technology in dense data storage systems. The demonstration platform includes four switch cards, which connect both optically and electronically to the electro-optical backplane in a chassis. These switch cards are controlled by a single board computer across a Compact PCI bus on the backplane. The electrooptical backplane is comprised of copper layers for power and low speed bus communication and one polymeric optical layer, wherein waveguides have been patterned by a direct laser writing scheme. The optical waveguide design includes densely arrayed multimode waveguides with a centre to centre pitch of 250μm between adjacent channels, multiple cascaded waveguide bends, non-orthogonal crossovers and in-plane connector interfaces. In addition, a novel passive alignment method has been employed to simplify high precision assembly of the optical receptacles on the backplane. The in-plane connector interface is based on a two lens free space coupling solution, which reduces susceptibility to contamination. Successful transfer of 10.3 Gb/s data along multiple waveguides in the electro-optical backplane has been demonstrated and characterised

FirstLight: Pluggable Optical Interconnect Technologies for Polymeric Electro-Optical Printed Circuit Boards in Data Centers

The protocol data rate governing data storage devices will increase to over 12 Gb/s by 2013 thereby imposing unmanageable cost and performance burdens on future digital data storage systems. The resulting performance bottleneck can be substantially reduced by conveying high-speed data optically instead of electronically. A novel active pluggable 82.5 Gb/s aggregate bit rate optical connector technology, the design and fabrication of a compact electro-optical printed circuit board to meet exacting specifications, and a method for low cost, high precision, passive optical assembly are presented. A demonstration platform was constructed to assess the viability of embedded electro-optical midplane technology in such systems including the first ever demonstration of a pluggable active optical waveguide printed circuit board connector. High-speed optical data transfer at 10.3125 Gb/s was demonstrated through a complex polymer waveguide interconnect layer embedded into a 262 mm × 240 mm × 4.3 mm electro-optical midplane. Bit error rates of less than 10-12 and optical losses as low as 6 dB were demonstrated through nine multimode polymer wave guides with an aggregate data bandwidth of 92.8125 Gb/s

RAID-2: Design and implementation of a large scale disk array controller

We describe the implementation of a large scale disk array controller and subsystem incorporating over 100 high performance 3.5 inch disk drives. It is designed to provide 40 MB/s sustained performance and 40 GB capacity in three 19 inch racks. The array controller forms an integral part of a file server that attaches to a Gb/s local area network. The controller implements a high bandwidth interconnect between an interleaved memory, an XOR calculation engine, the network interface (HIPPI), and the disk interfaces (SCSI). The system is now functionally operational, and we are tuning its performance. We review the design decisions, history, and lessons learned from this three year university implementation effort to construct a truly large scale system assembly

FirstLight: Pluggable Optical Interconnect Technologies for Polymeric Electro-Optical Printed Circuit Boards in Data Centers

The protocol data rate governing data storage devices will increase to over 12 Gb/s by 2013 thereby imposing unmanageable cost and performance burdens on future digital data storage systems. The resulting performance bottleneck can be substantially reduced by conveying high-speed data optically instead of electronically. A novel active pluggable 82.5 Gb/s aggregate bit rate optical connector technology, the design and fabrication of a compact electro-optical printed circuit board to meet exacting specifications, and a method for low cost, high precision, passive optical assembly are presented. A demonstration platform was constructed to assess the viability of embedded electro-optical midplane technology in such systems including the first ever demonstration of a pluggable active optical waveguide printed circuit board connector. High-speed optical data transfer at 10.3125 Gb/s was demonstrated through a complex polymer waveguide interconnect layer embedded into a 262 mm × 240 mm × 4.3 mm electro-optical midplane. Bit error rates of less than 10-12 and optical losses as low as 6 dB were demonstrated through nine multimode polymer wave guides with an aggregate data bandwidth of 92.8125 Gb/s

Quantifying SMT Decoupling Capacitor Placement in dc Power-Bus Design for Multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach

Quantifying Decoupling Capacitor Location

Decoupling capacitor location in DC power bus design is a critical design choice for which proven guidelines are not well established. The mutual inductance between two closely spaced vias can have a great impact on the coupling between an IC and a decoupling capacitor. This coupling is a function of the spacing between the IC and capacitor, and spacing between power and ground layers. The impact of the mutual inductance on decoupling, i.e., local versus global decoupling, was studied, using a circuit extraction approach based on a mixed-potential integral equation. Modeling indicates that local decoupling has benefits over global decoupling for certain ranges of IC/capacitor spacing and power layer thickness. Design curves for evaluating local decoupling benefits were generated, which can be used to guide surface mount technology (SMT) decoupling capacitor placement

EMC Analysis of an 18 LCD Monitor

This paper describes a case study covering the evaluation and reduction of the radiated EMI from an 18 inches Liquid Crystal Display (LCD) monitor. The evaluation was completed in two parts: first potential EMI sources at the Printed Circuit Board (PCB) level were identified, then the EMI antennas driven by these sources were analyzed. Methods for reducing the EMI were described in detail, and where applicable, those modifications were applied. Radiated measurements demonstrate the effectiveness of these recommendations