REALIZATION OF A VARIABLE RESOLUTION MODIFIED SEMIFLASH ADC BASED ON BIT SEGMENTATION SCHEME

A modified variable resolution semiflash ADC, based on ‘bit segmentation scheme’, is presented. Its speed and comparator count are identical to a normal flash ADC. An 8-bit ADC has 256 different bit combinations. Sixteen consecutive bit combinations from the MSB side – beginning with the first one, remain unaltered for such an ADC. It continues this way till the last group of sixteen bits. In the designed circuit, the four MSB and four LSB bits are determined in the first and second part of the clock. Following the same logic, the bits in a 16-bit ADC can be found out in only two clock cycles by employing only fifteen comparators. It implies that a higher resolution ADC can easily be determined with low power and small die area. It is tested in P-SIM Professional 9 for an 8-bit ADC and curves drawn to establish the validity of the proposal

An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers

Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThe rapid growth of wireless communications and the massive use of wireless end-user equipments have created a demand for low-cost, low-power and low-area devices with tight specifications imposed by standards. The advances in CMOS technology allows, nowadays, designers to implement circuits that work at high-frequencies, thus, allowing the complete implementation of RF front ends in a single chip. In this work, a co-design strategy for the implementation of a fully integrated CMOS receiver for use in the ISM band is presented. The main focus is given to the Mixer and the ADC blocks of the presented architecture. The traditional approach used in RF design requires 50 matching buffers and networks and AC coupling capacitors between Mixer inputs and LNA and LO outputs. The codesign strategy avoids the use of DC choke inductors for Mixer biasing, because it is possible to use the DC level from the output of the LNA and the LO to provide bias to the Mixer. Moreover, since the entire circuit is in the same chip and the Mixer inputs are transistors gates, we should consider voltage instead of power and avoid the 50 matching networks. The proposed ADC architecture relies on a 4-bit flash converter. The main goals are to achieve low-power and high sampling frequency. To meet these goals, parametric amplification based on MOS varactors is applied to reduce the offset voltage of the comparators, avoiding the traditional and power-consuming approach of active pre-amplification gain stages