Fractionally-addressed delay lines

While traditional implementations of variable-length digital delay lines are based on a circular buffer accessed by two pointers, we propose an implementation where a single fractional pointer is used both for read and write operations. On modern general-purpose architectures, the proposed method is nearly as efficient as the popularinterpolated circular buffer, and it behaves well for delay-length modulations commonly found in digital audio effects. The physical interpretation of the new implementation shows that it is suitable for simulating tension or density modulations in wave-propagating media.Comment: 11 pages, 19 figures, to be published in IEEE Transactions on Speech and Audio Processing Corrected ACM-clas

Maximally flat and least-square co-design of variable fractional delay filters for wideband software-defined radio

This paper describes improvements in a Farrow-structured variable fractional delay (FD) Lagrange filter for all-pass FD interpolation. The main idea is to integrate the truncated sinc into the Farrow structure of a Lagrange filter, in order that a superior FD approximation in the least-square sense can be achieved. Its primary advantages are the lower level of mean-square-error (MSE) over the whole FD range and the reduced implementation cost. Extra design parameters are introduced for making the trade-off between MSE and maximal flatness under different design requirements. Design examples are included, illustrating an MSE reduction of 50% compared to a classical Farrow-structured Lagrange interpolator while the implementation cost is reduced. This improved variable FD interpolation system is suitable for many applications, such as sample rate conversion, digital beamforming and timing synchronization in wideband software-defined radio (SDR) communications

Digital Filters

The new technology advances provide that a great number of system signals can be easily measured with a low cost. The main problem is that usually only a fraction of the signal is useful for different purposes, for example maintenance, DVD-recorders, computers, electric/electronic circuits, econometric, optimization, etc. Digital filters are the most versatile, practical and effective methods for extracting the information necessary from the signal. They can be dynamic, so they can be automatically or manually adjusted to the external and internal conditions. Presented in this book are the most advanced digital filters including different case studies and the most relevant literature

A new method for designing causal stable IIR variable fractional delay digital filters

This paper studies the design of causal stable Farrow-based infinite-impulse response (IIR) variable fractional delay digital filters (VFDDFs), whose subfilters have a common denominator. This structure has the advantages of reduced implementation complexity and avoiding undesirable transient response when tuning the spectral parameter in the Farrow structure. The design of such IIR VFDDFs is based on a new model reduction technique which is able to incorporate prescribed flatness and peak error constraints to the IIR VFDDF under the second order cone programming framework. Design example is given to demonstrate the effectiveness of the proposed approach. © 2007 IEEE.published_or_final_versio

Pascal-Interpolation-Based Noninteger Delay Filter and Low-Complexity Realization

This paper proposes a new method for designing the polynomial-interpolation-type noninteger-delay filter with a new structure formulation. Since the design formulation and the new realization structure are based on the discrete Pascal transform (DPT) and Pascal interpolation, we call the resulting filter Pascal noninteger-delay filter. The kth-order Pascal polynomial is used to pass through the given (k+1) data points in achieving the kth-order Pascal filter. The Pascal noninteger-delay filter is a real-time filter that consists of two sections, which can be realized into the front-section and the back-section. The front-section contains multiplication-free digital filters, and the number of multiplications in the back-section just linearly increases as order becomes high. Since the new Pascal filter has low complexity and structure can adjust non-integer delay online, it is more suited for fast delay tuning. Consequently, the polynomial-interpolation-type delay filter can be achieved by using the Pascal approach with high efficiency and low-complexity structure

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

Low power two-channel PR QMF bank using CSD coefficients and FPGA implementation

Finite impulse response (FIR) filter is a fundamental component in digital signal processing. Two-channel perfect reconstruction (PR) QMF banks are widely used in many applications, such as image coding, speech processing and communications. A practical lattice realization of two-channel QMF bank is developed in this thesis for dealing with the wide dynamic range of intermediate results in lattice structure. To achieve low complexity and low power consumption of two-channel perfect reconstruction QMF bank, canonical signed digit (CSD) number system is used for representing lattice coefficients in FPGA implementation. Utilization of CSD number system in lattice structures leads to more efficient hardware implementation. Many fixed-point simulations were done in Matlab in order to obtain the proper fixed-point word-length for different signals. Finally, FPGA implementation results show that perfect reconstruction signal is obtained by using the proposed method. Furthermore, the power consumption using CSD number system for representing lattice coefficients is less than that obtained by using two\u27s complement number system in two-channel QMF bank. A low complexity and low power two-channel PR QMF bank using CSD coefficients was realized