A Comprehensive Review on Convex and Concave Corners in Silicon Bulk Micromachining based on Anisotropic Wet Chemical Etching

Wet anisotropic etching based silicon micromachining is an important technique to fabricate freestanding (e.g. cantilever) and fixed (e.g. cavity) structures on different orientation silicon wafers for various applications in microelectromechanical systems (MEMS). {111} planes are the slowest etch rate plane in all kinds of anisotropic etchants and therefore, a prolonged etching always leads to the appearance of {111} facets at the sidewalls of the fabricated structures. In wet anisotropic etching, undercutting occurs at the extruded corners and the curved edges of the mask patterns on the wafer surface. The rate of undercutting depends upon the type of etchant and the shape of mask edges and corners. Furthermore, the undercutting takes place at the straight edges if they do not contain {111} planes. {100} and {110} silicon wafers are most widely used in MEMS as well as microelectronics fabrication. This paper reviews the fabrication techniques of convex corner on {100} and {110} silicon wafers using anisotropic wet chemical etching. Fabrication methods are classified mainly into two major categories: corner compensation method and two-steps etching technique . In corner compensation method, extra mask pattern is added at the corner. Due to extra geometry, etching is delayed at the convex corner and hence the technique relies on time delayed etching. The shape and size of the compensating design strongly depends on the type of etchant, etching depth and the orientation of wafer surface. In this paper, various kinds of compensating designs published so far are discussed. Two-step etching method is employed for the fabrication of perfect convex corners. Since the perfectly sharp convex corner is formed by the intersection of {111} planes, each step of etching defines one of the facets of convex corners. In this method, two different ways are employed to perform the etching process and therefore can be subdivided into two parts. In one case, lithography step is performed after the first step of etching, while in the second case, all lithography steps are carried out before the etching process, but local oxidation of silicon (LOCOS) process is done after the first step of etching. The pros and cons of all techniques are discussed

Integrated Lithographic Molding for Microneedle-Based Devices

This paper presents a new fabrication method consisting of lithographically defining multiple layers of high aspect-ratio photoresist onto preprocessed silicon substrates and release of the polymer by the lost mold or sacrificial layer technique, coined by us as lithographic molding. The process methodology was demonstrated fabricating out-of-plane polymeric hollow microneedles. First, the fabrication of needle tips was demonstrated for polymeric microneedles with an outer diameter of 250 mum, through-hole capillaries of 75-mum diameter and a needle shaft length of 430 mum by lithographic processing of SU-8 onto simple v-grooves. Second, the technique was extended to gain more freedom in tip shape design, needle shaft length and use of filling materials. A novel combination of silicon dry and wet etching is introduced that allows highly accurate and repetitive lithographic molding of a complex shape. Both techniques consent to the lithographic integration of microfluidic back plates forming a patch-type device. These microneedle-integrated patches offer a feasible solution for medical applications that demand an easy to use point-of-care sample collector, for example, in blood diagnostics for lithium therapy. Although microchip capillary electrophoresis glass devices were addressed earlier, here, we show for the first time the complete diagnostic method based on microneedles made from SU-8

Bulk micromachining of silicon for MOEMS prototype

In this dissertation, the optical application of silicon micromachining technology was investigated in order to create the three-dimensional microstructures that can be used as the components for the MOEMS prototype. These microstructures were designed and fabricated by utilizing corner compensation techniques and silicon bulk micromachining technologies. The fabricated microstructures are silicon mirror arrays that have a 1250 μm etch depth and through-holes across the OE-MCM substrate that has sixteen-fan-out OCDN on front side and a 1mm thickness. Guided-wave OCDN on MCMs are designed and fabricated to meet the high-speed clocking requirements of next-generation digital systems through a realization of superior network bandwidth, low power consumption, and large fan-out capabilities. Two fabricated components were assembled to build the MOEMS prototype. From the fiber-to-waveguide butt coupler, the light signal is launched on the waveguide core, and the signal travels and splits along the waveguide. Then, the light signals reflect at the micromachined silicon mirrors which are located in the sixteen fan-out nodes. This device was characterized by measuring the excess loss at the sixteen fan-out nodes at the wavelengths of 1310 nm and 1550 nm. The results show low loss signal propagation and signal uniformity

Determination of precise crystallographic directions for mask alignment in wet bulk micromachining for MEMS

In wet bulk micromachining, the etching characteristics are orientation dependent. As a result, prolonged etching of mask openings of any geometric shape on both Si{100} and Si{110} wafers results in a structure defined by the slowest etching planes. In order to fabricate microstructures with high dimensional accuracy, it is vital to align the mask edges along the crystal directions comprising of these slowest etching planes. Thus, precise alignment of mask edges is important in micro/nano fabrication. As a result, the determination of accurate crystal directions is of utmost importance and is in fact the first step to ensure dimensionally accurate microstructures for improved performance. In this review article, we have presented a comprehensive analysis of different techniques to precisely determine the crystallographic directions. We have covered various techniques proposed in the span of more than two decades to determine the crystallographic directions on both Si{100} and Si{110} wafers. Apart from a detailed discussion of each technique along with their design and implementation, we have provided a critical analysis of the associated constraints, benefits and shortcomings. We have also summed up the critical aspects of each technique and presented in a tabular format for easy reference for readers. This review article comprises of an exhaustive discussion and is a handy reference for researchers who are new in the field of wet anisotropic etching or who want to get abreast with the techniques of determination of crystal directions

Photoelectrochemical etching of isolated, high aspect ratio micorstructures in n-type silicon (100)

Three-dimensional integration techniques have become increasingly popular to meet the ever rising demand of high capacity and reduced package size in microelectronics devices. Through Silicon Vias (TSVs) offer an efficient method to achieve 3D packaging with shorter interconnection length and higher interconnect density relative to conventional wire bonding. Wet electrochemical etching is a simple technique which may be used to create deep structures in silicon and is relatively low cost compared with Reactive Ion Etching or Laser drilling. Historically, a primary challenge is passivating TSV (macropore, microstructure) sidewalls against etching at sidewall thickness greater than twice the depletion region width. Lehmann et al created macropores in n-type silicon (40 Ω-cm) with sidewall thickness ~ six times depletion region width, however the wall surface smoothness differed from the macropores passivated by the depletion region. In this research, an attempt was made to create isolated (sidewall thickness = ∞ times the depletion region width) microstructures in patterned n-type silicon (100). For the first time, high aspect ratio (~5:1) deep microstructures with non-porous sidewalls at isolated pitches (\u3e100 µm) are demonstrated using frontside illumination with photoelectrochemical etching. Further, the microstructure aspect ratio is observed to increase with etch duration. While literature on backside illumination illustrates porous sidewalls at isolated pitches, results from this study show frontside illumination can be used to create non-porous microstructures at large pitches. The microstructure etch rate is a function of light intensity and supporting electrolyte composition whereas the microstructure sidewall etching is demonstrated to be a function of applied anodic bias. Anodic bias controls the depletion region width which governs the dominance of drift and diffusion currents. Isolated microstructures are obtained at a low anodic bias where silicon dissolution is controlled by the diffusion current. The microstructure surface smoothness is affected by incident light wavelength; sidewall roughness is minimized by conducting the dissolution reaction with photons having shallower absorption depth in silicon. The work shows photoelectrochemical etching of isolated, anisotropic, high aspect ratio microstructures is possible using frontside illumination with low wavelength light at low anodic bias

A Novel Batch-Processing Method for Accurate Crystallographic Axis Alignment

A new method for the accurate alignment of lithographically-defined patterns to the crystallographic axes of substrates is presented. We provide a lower (worst-case) limit of the achievable high aspect ratio using anisotropic wet chemical silicon etch for deep trenches. The method uses the fact that the intensity of light reflected from two sets of gratings, one on the photomask and the other on the substrate, is a sharp function of their relative angular misalignment. By using pre-etched gratings on the substrate formed by wet anisotropic etching, alignment accuracies better than 50 millidegrees with respect to silicon crystallographic axes have been demonstrated. Two types of microstructures—trenches with an aspect ratio \u3e90:1 and silicon nanowires with widthsfacets—have been fabricated using i-line lithography to illustrate some applications of this alignment method. This all-optical method is readily applicable to industry-standard optical lithography and avoids the need for any individualized process steps, enabling cost-effective micro/nanostructure manufacturing