Two Transistor Current Mode Active Pixel Sensor

A novel current mode active pixel sensor for high resolution imaging is presented. The photo pixel is composed of a photodiode and two transistors: reset and transconductance amplifier transistor. The switch transistor is moved outside the pixel, allowing for lower pixel pitch and increased linearity of the output photocurrent. The increased linearity of the image sensor has greatly reduced spatial variations across the image after correlated double sampling and the column fix pattern noise is 0.35% of the saturated current. A discussion on theoretical temporal noise limitations of this design is also presented

Current mode monolithic active pixel sensor with correlated double sampling for charged particle detection

A monolithic active pixel sensor operating in current mode for charged particle detection is described. The sensing element in each pixel is an n-well/p-sub diode with a PMOS transistor integrated in an n-well. The drop of the n-well potential from the collection of charge modulates the transistor channel current. Each pixel features two current mode memory cells. The subtraction of distant-in-time samples frees the signal of fixed pattern noise (FPN) and of the correlated low-frequency temporal noise components, resulting in extraction of the particle footprint. The subtraction circuits are placed at each column end. A transimpedance amplifier, integrating in sequence two current samples and subtracting the results in an arithmetic operation, was adopted. The integrated version of the transimpedance amplifier, designed with a maximized conversion gain, is burdened by a risk of an early saturation, imperiling its operation, if the dispersions of the dc current component are too big. The degree of dispersions could not be estimated during the design. Some number of columns is available as a backup with the direct current readout. An external realization of the subtracting circuit, based on the same principle, is used to process direct output columns. The concept of the data acquisition setup developed, the tested performance of an array of cells, and the processing circuitry are described

Overview of ionizing radiation effects in image sensors fabricated in a deep-submicrometer CMOS imaging technology

An overview of ionizing radiation effects in imagers manufactured in a 0.18-μm CMOS image sensor technology is presented. Fourteen types of image sensors are characterized and irradiated by a 60Co source up to 5 kGy. The differences between these 14 designs allow us to separately estimate the effect of ionizing radiation on microlenses, on low- and zero-threshold-voltage MOSFETs and on several pixel layouts using P+ guard-rings and edgeless transistors. After irradiation, wavelength dependent responsivity drops are observed. All the sensors exhibit a large dark current increase attributed to the shallow trench isolation that surrounds the photodiodes. Saturation voltage rises and readout chain gain variations are also reported. Finally, the radiation hardening perspectives resulting from this paper are discussed

Novel readout circuit architecture for CMOS image sensors minimizing RTS noise

This letter presents a novel readout architecture and its associated readout sequence for complementary metal–oxide– semiconductor (CMOS) image sensors (CISs) based on switch biasing techniques in order to reduce noisy pixel numbers induced by in-pixel source-follower transistor random telegraph signal noise. Measurement results done on a test image sensor designed with 0.35-μm CIS technology demonstrate an efficient reduction of noisy pixel numbers without a pixel performance decrease

Low-frequency noise impact on CMOS image sensors

CMOS image sensors are nowadays extensively used in imaging applications even for high-end applications. This is really possible thanks to a reduction of noise obtained, among others, by Correlated Double Sampling (CDS) readout. Random Telegraph Signal (RTS) noise has thus become an issue for low light level applications especially in the context of downscaling transistor size. This paper describes the analysis of in-pixel source follower transistor RTS noise filtering by CDS circuit. The measurement of a non Gaussian distribution with a positive skew of image sensor output noise is analysed. Impact of dimensions (W and L) of the in-pixel source follower is demonstrated. Circuit to circuit pixel output noise dispersion on 12 circuits coming from 3 different wafers is also analysed and weak dispersion is seen

A Bio-Inspired Vision Sensor With Dual Operation and Readout Modes

This paper presents a novel event-based vision sensor with two operation modes: intensity mode and spatial contrast detection. They can be combined with two different readout approaches: pulse density modulation and time-to-first spike. The sensor is conceived to be a node of an smart camera network made up of several independent an autonomous nodes that send information to a central one. The user can toggle the operation and the readout modes with two control bits. The sensor has low latency (below 1 ms under average illumination conditions), low power consumption (19 mA), and reduced data flow, when detecting spatial contrast. A new approach to compute the spatial contrast based on inter-pixel event communication less prone to mismatch effects than diffusive networks is proposed. The sensor was fabricated in the standard AMS4M2P 0.35-um process. A detailed system-level description and experimental results are provided.Office of Naval Research (USA) N00014-14-1-0355Ministerio de Economía y Competitividad TEC2012- 38921-C02-02, P12-TIC-2338, IPT-2011-1625-43000

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $\mu$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $\Omega$cm for the substrate and tested in standalone mode. The results show a rise time of $\sim20$ ns, charge gain of $190$ mV/ke$^{-}$ and $\sim40$ e$^{-}$ RMS noise for a power consumption of $4.8$ $\mu$W/pixel. The main design aspects, as well as standalone measurement results, are presented.Comment: 13 pages, 13 figures, 2 tables. Work carried out in the framework of the CLICdp collaboratio

Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT’s connected in a Darlington structure. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], [2], incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-µm technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm2, with a power consumption down to 105 µW/unit and image processing times below 2 µs

RTS noise impact in CMOS image sensors readout circuit

CMOS image sensors are nowadays widely used in imaging applications even for high end applications. This is really possible thanks to a reduction of noise obtained, among others, by Correlated Double Sampling (CDS) readout. Random Telegraph Signal (RTS) noise has thus become an issue for low light level applications especially in the context of downscaling transistor dimension. This paper describes the analysis of in-pixel source follower transistor RTS noise filtering by CDS circuit. The measurement of a non Gaussian distribution with a positive skew of image sensor output noise is analysed and dimension (W and L) impact of the in-pixel source follower is analysed