281 research outputs found
Two Hardware Implementations of the Exhaustive Synthetic AER Generation Method
Address-Event-Representation (AER) is a communications protocol
for transferring images between chips, originally developed for bio-inspired
image processing systems. In [6], [5] various software methods for synthetic
AER generation were presented. But in neuro-inspired research field, hardware
methods are needed to generate AER from laptop computers. In this paper two
real time implementations of the exhaustive method, proposed in [6], [5], are
presented. These implementations can transmit, through AER bus, images
stored in a computer using USB-AER board developed by our RTCAR group
for the CAVIAR EU project.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0
Real-time motor rotation frequency detection with event-based visual and spike-based auditory AER sensory integration for FPGA
Multisensory integration is commonly
used in various robotic areas to collect more
environmental information using different and
complementary types of sensors. Neuromorphic
engineers mimics biological systems behavior to
improve systems performance in solving engineering
problems with low power consumption. This work
presents a neuromorphic sensory integration scenario
for measuring the rotation frequency of a motor using
an AER DVS128 retina chip (Dynamic Vision Sensor)
and a stereo auditory system on a FPGA completely
event-based. Both of them transmit information with
Address-Event-Representation (AER). This
integration system uses a new AER monitor hardware
interface, based on a Spartan-6 FPGA that allows two
operational modes: real-time (up to 5 Mevps through
USB2.0) and data logger mode (up to 20Mevps for
33.5Mev stored in onboard DDR RAM). The sensory
integration allows reducing prediction error of the
rotation speed of the motor since audio processing
offers a concrete range of rpm, while DVS can be
much more accurate.Ministerio de Economía y Competitividad TEC2012-37868-C04-02/0
Embedding Multi-Task Address-Event- Representation Computation
Address-Event-Representation, AER, is a communication protocol that is
intended to transfer neuronal spikes between bioinspired chips. There are
several AER tools to help to develop and test AER based systems, which may
consist of a hierarchical structure with several chips that transmit spikes
among them in real-time, while performing some processing. Although these
tools reach very high bandwidth at the AER communication level, they require
the use of a personal computer to allow the higher level processing of the
event information. We propose the use of an embedded platform based on a
multi-task operating system to allow both, the AER communication and
processing without the requirement of either a laptop or a computer. In this
paper, we present and study the performance of an embedded multi-task AER
tool, connecting and programming it for processing Address-Event
information from a spiking generator.Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
Spike-based control monitoring and analysis with Address Event Representation
Neuromorphic engineering tries to mimic biological
information processing. Address-Event Representation (AER) is
a neuromorphic communication protocol for spiking neurons
between different chips. We present a new way to drive robotic
platforms using spiking neurons. We have simulated spiking
control models for DC motors, and developed a mobile robot
(Eddie) controlled only by spikes. We apply AER to the robot
control, monitoring and measuring the spike activity inside the
robot. The mobile robot is controlled by the AER-Robot tool,
and the AER information is sent to a PC using the
USBAERmini2 interface.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0
On the Designing of Spikes Band-Pass Filters for FPGA
In this paper we present two implementations of spike-based bandpass
filters, which are able to reject out-of-band frequency components in the
spike domain. First one is based on the use of previously designed spike-based
low-pass filters. With this architecture the quality factor, Q, is lower than 0.5.
The second implementation is inspired in the analog multi-feedback filters
(MFB) topology, it provides a higher than 1 Q factor, and ideally tends to
infinite. These filters have been written in VHLD, and synthesized for FPGA.
Two spike-based band-pass filters presented take advantages of the spike rate
coded representation to perform a massively parallel processing without complex
hardware units, like floating point arithmetic units, or a large memory. These low
requirements of hardware allow the integration of a high number of filters inside
a FPGA, allowing to process several spike coded signals fully in parallel.Ministerio de Ciencia e Innovación TEC2009-10639-C04-0
Building Blocks for Spikes Signals Processing
Neuromorphic engineers study models and
implementations of systems that mimic neurons behavior in the
brain. Neuro-inspired systems commonly use spikes to
represent information. This representation has several
advantages: its robustness to noise thanks to repetition, its
continuous and analog information representation using digital
pulses, its capacity of pre-processing during transmission time,
... , Furthermore, spikes is an efficient way, found by nature, to
codify, transmit and process information. In this paper we
propose, design, and analyze neuro-inspired building blocks
that can perform spike-based analog filters used in signal
processing. We present a VHDL implementation for FPGA.
Presented building blocks take advantages of the spike rate
coded representation to perform a massively parallel processing
without complex hardware units, like floating point arithmetic
units, or a large memory. Those low requirements of hardware
allow the integration of a high number of blocks inside a FPGA,
allowing to process fully in parallel several spikes coded signals.Junta de Andalucía P06-TIC-O1417Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
AER-based robotic closed-loop control system
Address-Event-Representation (AER) is an
asynchronous protocol for transferring the information of
spiking neuro-inspired systems. Actually AER systems are able
to see, to ear, to process information, and to learn. Regarding to
the actuation step, the AER has been used for implementing
Central Pattern Generator algorithms, but not for controlling
the actuators in a closed-loop spike-based way. In this paper we
analyze an AER based model for a real-time neuro-inspired
closed-loop control system. We demonstrate it into a differential
control system for a two-wheel vehicle using feedback AER
information. PFM modulation has been used to power the DC
motors of the vehicle and translation into AER of encoder
information is also presented for the close-loop. A codesign
platform (called AER-Robot), based into a Xilinx Spartan 3
FPGA and an 8051 USB microcontroller, with power stages for
four DC motors has been used for the demonstrator.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0
AER Spiking Neuron Computation on GPUs: The Frame-to-AER Generation
Neuro-inspired processing tries to imitate the nervous system and may
resolve complex problems, such as visual recognition. The spike-based philosophy
based on the Address-Event-Representation (AER) is a neuromorphic interchip
communication protocol that allows for massive connectivity between neurons.
Some of the AER-based systems can achieve very high performances in real-time
applications. This philosophy is very different from standard image processing,
which considers the visual information as a succession of frames. These frames
need to be processed in order to extract a result. This usually requires very
expensive operations and high computing resource consumption. Due to its relative
youth, nowadays AER systems are short of cost-effective tools like emulators,
simulators, testers, debuggers, etc. In this paper the first results of a CUDA-based
tool focused on the functional processing of AER spikes is presented, with the aim
of helping in the design and testing of filters and buses management of these
systems.Ministerio de Educación y Ciencia TEC2009-10639-C04-0
Sound Recognition System Using Spiking and MLP Neural Networks
In this paper, we explore the capabilities of a sound classification
system that combines a Neuromorphic Auditory System for feature extraction
and an artificial neural network for classification. Two models of neural network
have been used: Multilayer Perceptron Neural Network and Spiking Neural
Network. To compare their accuracies, both networks have been developed and
trained to recognize pure tones in presence of white noise. The spiking neural
network has been implemented in a FPGA device. The neuromorphic auditory
system that is used in this work produces a form of representation that is analogous
to the spike outputs of the biological cochlea. Both systems are able to distinguish
the different sounds even in the presence of white noise. The recognition system
based in a spiking neural networks has better accuracy, above 91 %, even when
the sound has white noise with the same power.Ministerio de Economía y Competitividad TEC2012-37868-C04-02Junta de Andalucía P12-TIC-130
A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
This paper presents a new architecture, design
flow, and field-programmable gate array (FPGA) implementation
analysis of a neuromorphic binaural auditory sensor, designed
completely in the spike domain. Unlike digital cochleae that
decompose audio signals using classical digital signal processing
techniques, the model presented in this paper processes information
directly encoded as spikes using pulse frequency modulation
and provides a set of frequency-decomposed audio information
using an address-event representation interface. In this case,
a systematic approach to design led to a generic process for
building, tuning, and implementing audio frequency decomposers
with different features, facilitating synthesis with custom features.
This allows researchers to implement their own parameterized
neuromorphic auditory systems in a low-cost FPGA in order to
study the audio processing and learning activity that takes place
in the brain. In this paper, we present a 64-channel binaural
neuromorphic auditory system implemented in a Virtex-5 FPGA
using a commercial development board. The system was excited
with a diverse set of audio signals in order to analyze its response
and characterize its features. The neuromorphic auditory system
response times and frequencies are reported. The experimental
results of the proposed system implementation with 64-channel
stereo are: a frequency range between 9.6 Hz and 14.6 kHz
(adjustable), a maximum output event rate of 2.19 Mevents/s,
a power consumption of 29.7 mW, the slices requirements
of 11 141, and a system clock frequency of 27 MHz.Ministerio de Economía y Competitividad TEC2012-37868-C04-02Junta de Andalucía P12-TIC-130
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