Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed

An instruction systolic array architecture for multiple neural network types

Modern electronic systems, especially sensor and imaging systems, are beginning to incorporate their own neural network subsystems. In order for these neural systems to learn in real-time they must be implemented using VLSI technology, with as much of the learning processes incorporated on-chip as is possible. The majority of current VLSI implementations literally implement a series of neural processing cells, which can be connected together in an arbitrary fashion. Many do not perform the entire neural learning process on-chip, instead relying on other external systems to carry out part of the computation requirements of the algorithm. The work presented here utilises two dimensional instruction systolic arrays in an attempt to define a general neural architecture which is closer to the biological basis of neural networks - it is the synapses themselves, rather than the neurons, that have dedicated processing units. A unified architecture is described which can be programmed at the microcode level in order to facilitate the processing of multiple neural network types. An essential part of neural network processing is the neuron activation function, which can range from a sequential algorithm to a discrete mathematical expression. The architecture presented can easily carry out the sequential functions, and introduces a fast method of mathematical approximation for the more complex functions. This can be evaluated on-chip, thus implementing the entire neural process within a single system. VHDL circuit descriptions for the chip have been generated, and the systolic processing algorithms and associated microcode instruction set for three different neural paradigms have been designed. A software simulator of the architecture has been written, giving results for several common applications in the field

VLSI design of a twin register file for reducing the effects of conditional branches in a pipelined architecture

Pipelining is a major organizational technique which has been used by computer engineers to enhance the performance of computers. Pipelining improves the performance of computer systems by exploiting the instruction level parallelism of a program. In a pipelined processor the execution of instructions is overlapped, and each instruction is executed in a different stage of the pipeline. Most pipelined architectures are based on a sequential model of program execution in which a program counter sequences through instructions one by one.A fundamental disadvantage of pipelined processing is the loss incurred due to conditional branches. When a conditional branch instruction is encountered, more than one possible paths are following the instruction. The correct path can be known only upon the completion of the conditional branch instruction. The execution of the next instruction following a conditional branch cannot be started until the conditional branch instruction is resolved, resulting in stalling of the pipeline. One approach to avoid stalling is to predict the path to be executed and continue the execution of instructions along the predicted path. But in this case an incorrect prediction results in the execution of incorrect instructions. Hence . the results of these incorrect instructions have to be purged. Also, the instructions in the various stages of the pipeline must be removed and the pipeline has to start fetching instructions from the correct path. Thus incorrect prediction involves a flushing of the pipeline. This thesis proposes a twin processor architecture for reducing the effects of conditional branches. In such an architecture, both the paths following a conditional branch are executed simultaneously on two processors. When the conditional branch is resolved, the results of the incorrect path are discarded. Such an architecture requires a special purpose twin register file. It is the purpose of this thesis to design a twin register file consisting of two register files which can be independently accessed by the two processors. Each of the register files also has the capability of being copied into the other, making the design of the twin register file a complicated issue. The special pwpose twin register file is designed using layout tools Lager and Magic. The twin register file consists of two three-port register files which are capable of executing the 'read', 'write' and 'transfer' operations. The transfer of data from one register f.tle to another is accomplished in a single phase of the cl<X!k. The functionality of a 32-word-by-16-bit twin register file is verified by simulating it on IRSIM. The timing requirements for the read, write and transfer operations are detennined by simulating the twin register file on SPICE.Electrical Engineerin

Towards Efficient and Trustworthy AI Through Hardware-Algorithm-Communication Co-Design

Artificial intelligence (AI) algorithms based on neural networks have been designed for decades with the goal of maximising some measure of accuracy. This has led to two undesired effects. First, model complexity has risen exponentially when measured in terms of computation and memory requirements. Second, state-of-the-art AI models are largely incapable of providing trustworthy measures of their uncertainty, possibly `hallucinating' their answers and discouraging their adoption for decision-making in sensitive applications. With the goal of realising efficient and trustworthy AI, in this paper we highlight research directions at the intersection of hardware and software design that integrate physical insights into computational substrates, neuroscientific principles concerning efficient information processing, information-theoretic results on optimal uncertainty quantification, and communication-theoretic guidelines for distributed processing. Overall, the paper advocates for novel design methodologies that target not only accuracy but also uncertainty quantification, while leveraging emerging computing hardware architectures that move beyond the traditional von Neumann digital computing paradigm to embrace in-memory, neuromorphic, and quantum computing technologies. An important overarching principle of the proposed approach is to view the stochasticity inherent in the computational substrate and in the communication channels between processors as a resource to be leveraged for the purpose of representing and processing classical and quantum uncertainty

A Computational Model for Quantum Measurement

Is the dynamical evolution of physical systems objectively a manifestation of information processing by the universe? We find that an affirmative answer has important consequences for the measurement problem. In particular, we calculate the amount of quantum information processing involved in the evolution of physical systems, assuming a finite degree of fine-graining of Hilbert space. This assumption is shown to imply that there is a finite capacity to sustain the immense entanglement that measurement entails. When this capacity is overwhelmed, the system's unitary evolution becomes computationally unstable and the system suffers an information transition (`collapse'). Classical behaviour arises from the rapid cycles of unitary evolution and information transitions. Thus, the fine-graining of Hilbert space determines the location of the `Heisenberg cut', the mesoscopic threshold separating the microscopic, quantum system from the macroscopic, classical environment. The model can be viewed as a probablistic complement to decoherence, that completes the measurement process by turning decohered improper mixtures of states into proper mixtures. It is shown to provide a natural resolution to the measurement problem and the basis problem.Comment: 24 pages; REVTeX4; published versio