The NASA SBIR product catalog

The purpose of this catalog is to assist small business firms in making the community aware of products emerging from their efforts in the Small Business Innovation Research (SBIR) program. It contains descriptions of some products that have advanced into Phase 3 and others that are identified as prospective products. Both lists of products in this catalog are based on information supplied by NASA SBIR contractors in responding to an invitation to be represented in this document. Generally, all products suggested by the small firms were included in order to meet the goals of information exchange for SBIR results. Of the 444 SBIR contractors NASA queried, 137 provided information on 219 products. The catalog presents the product information in the technology areas listed in the table of contents. Within each area, the products are listed in alphabetical order by product name and are given identifying numbers. Also included is an alphabetical listing of the companies that have products described. This listing cross-references the product list and provides information on the business activity of each firm. In addition, there are three indexes: one a list of firms by states, one that lists the products according to NASA Centers that managed the SBIR projects, and one that lists the products by the relevant Technical Topics utilized in NASA's annual program solicitation under which each SBIR project was selected

Intégration 3D de dispositifs SET dans le Back-End-Of-Line en technologies CMOS 28 nm pour le développement de capteurs ultra basse consommation

La forte demande et le besoin d’intégration hétérogène de nouvelles fonctionnalités dans les systèmes mobiles et autonomes, tels que les mémoires, capteurs, et interfaces de communication doit prendre en compte les problématiques d’hétérogénéité, de consommation d’énergie et de dissipation de chaleur. Les systèmes mobiles intelligents sont déjà dotés de plusieurs composants de type capteur comme les accéléromètres, les thermomètres et les détecteurs infrarouge. Cependant, jusqu’à aujourd’hui l’intégration de capteurs chimiques dans des systèmes compacts sur puce reste limitée pour des raisons de consommation d’énergie et dissipation de chaleur principalement. La technologie actuelle et fiable des capteurs de gaz, les résistors à base d’oxyde métallique et les MOSFETs (Metal Oxide Semiconductor- Field Effect Transistors) catalytiques sont opérés à de hautes températures de 200–500 °C et 140–200 °C, respectivement. Les transistors à effet de champ à grille suspendu (SG-FETs pour Suspended Gate-Field Effect Transistors) offrent l’avantage d’être sensibles aux molécules gazeuses adsorbées aussi bien par chemisorption que par physisorption, et sont opérés à température ambiante ou légèrement au-dessus. Cependant l’intégration de ce type de composant est problématique due au besoin d’implémenter une grille suspendue et l’élargissement de la largeur du canal pour compenser la détérioration de la transconductance due à la faible capacité à travers le gap d’air. Les transistors à double grilles sont d’un grand intérêt pour les applications de détection de gaz, car une des deux grilles est fonctionnalisée et permet de coupler capacitivement au canal les charges induites par l’adsorption des molécules gazeuses cibles, et l’autre grille est utilisée pour le contrôle du point d’opération du transistor sans avoir besoin d’une structure suspendue. Les transistors monoélectroniques (les SETs pour Single Electron Transistors) présentent une solution très prometteuse grâce à leur faible puissance liée à leur principe de fonctionnement basé sur le transport d’un nombre réduit d’électrons et leur faible niveau de courant. Le travail présenté dans cette thèse fut donc concentré sur la démonstration de l’intégration 3D monolithique de SETs sur un substrat de technologie CMOS (Complementary Metal Oxide Semiconductor) pour la réalisation de la fonction capteurs de gaz très sensible et ultra basse consommation d’énergie. L’approche proposée consiste à l’intégration de SETs métalliques à double grilles dans l’unité de fabrication finale BEOL (Back-End-Of-Line) d’une technologie CMOS à l’aide du procédé nanodamascene. Le système sur puce profitera de la très élevée sensibilité à la charge électrique du transistor monoélectronique, ainsi que le traitement de signal et des données à haute vitesse en utilisant une technologie de pointe CMOS disponible. Les MOSFETs issus de la technologie FD-SOI (Fully Depleted-Silicon On Insulator) sont une solution très attractive à cause de leur pouvoir d’amplification du signal quand ils sont opérés dans le régime sous-le-seuil. Ces dispositifs permettent une très haute densité d’intégration due à leurs dimensions nanométriques et sont une technologie bien mature et modélisée. Ce travail se concentre sur le développement d’un procédé de fonctionnalisation d’un MOSFET FD-SOI comme démonstration du concept du capteur de gaz à base de transistor à double grilles. La sonde Kelvin a été la technique privilégiée pour la caractérisation des matériaux sensibles par le biais de mesure de la variation du travail de sortie induite par l’adsorption de molécules de gaz. Dans ce travail, une technique de caractérisation des matériaux sensibles alternative basée sur la mesure de la charge de surface est discutée. Pour augmenter la surface spécifique de l’électrode sensible, un nouveau concept de texturation de surface est présenté. Le procédé est basé sur le dépôt de réseaux de nanotubes de carbone multi-parois par pulvérisation d’une suspension de ces nanotubes. Les réseaux déposés servent de «squelettes» pour le matériau sensible. L’objectif principal de cette thèse de doctorat peut être divisé en 4 parties : (1) la modélisation et simulation de la réponse d’un capteur de gaz à base de SET à double grilles ou d’un MOSFET FD-SOI, et l’estimation de la sensibilité ainsi que la puissance consommée; (2) la caractérisation de la sensibilité du Pt comme couche sensible pour la détection du H[indice inférieur 2] par la technique de mesure de charge de surface, et le développement du procédé de texturation de surface de la grille fonctionnalisée avec les réseaux de nanotubes de carbone; (3) le développement et l’optimisation du procédé de fabrication des SETs à double grilles dans l’entité BEOL d’un substrat CMOS; et (4) la fonctionnalisation d’un MOSFET FD-SOI avec du Pt pour réaliser la fonction de capteur de H[indice inférieur 2].Abstract : The need of integration of new functionalities on mobile and autonomous electronic systems has to take into account all the problematic of heterogeneity together with energy consumption and thermal dissipation. In this context, all the sensing or memory components added to the CMOS (Complementary Metal Oxide Semiconductor) processing units have to respect drastic supply energy requirements. Smart mobile systems already incorporate a large number of embedded sensing components such as accelerometers, temperature sensors and infrared detectors. However, up to now, chemical sensors have not been fully integrated in compact systems on chips. Integration of gas sensors is limited since most used and reliable gas sensors, semiconducting metal oxide resistors and catalytic metal oxide semiconductor- field effect transistors (MOSFETs), are generally operated at high temperatures, 200–500 °C and 140–200° C, respectively. The suspended gate-field effect transistor (SG-FET)-based gas sensors offer advantages of detecting chemisorbed, as well as physisorbed gas molecules and to operate at room temperature or slightly above it. However they present integration limitations due to the implementation of a suspended gate electrode and augmented channel width in order to overcome poor transconductance due to the very low capacitance across the airgap. Double gate-transistors are of great interest for FET-based gas sensing since one functionalized gate would be dedicated for capacitively coupling of gas induced charges and the other one is used to bias the transistor, without need of airgap structure. This work discusses the integration of double gate-transistors with CMOS devices for highly sensitive and ultra-low power gas sensing applications. The use of single electron transistors (SETs) is of great interest for gas sensing applications because of their key properties, which are its ultra-high charge sensitivity and the ultra-low power consumption and dissipation, inherent to the fundamental of their operation based on the transport of a reduced number of charges. Therefore, the work presented in this thesis is focused on the proof of concept of 3D monolithic integration of SETs on CMOS technology for high sensitivity and ultra-low power gas sensing functionality. The proposed approach is to integrate metallic double gate-single electron transistors (DG-SETs) in the Back-End-Of-Line (BEOL) of CMOS circuits (within the CMOS interconnect layers) using the nanodamascene process. We take advantage of the hyper sensitivity of the SET to electric charges as well from CMOS circuits for high-speed signal processing. Fully depleted-silicon on insulator (FD-SOI) MOSFETs are very attractive devices for gas sensing due to their amplification capability when operated in the sub-threshold regime which is the strongest asset of these devices with respect to the FET-based gas sensor technology. In addition these devices are of a high interest in terms of integration density due to their small size. Moreover FD-SOI FETs is a mature and well-modelled technology. We focus on the functionalization of the front gate of a FD-SOI MOSFET as a demonstration of the DGtransistor- based gas sensor. Kelvin probe has been the privileged technique for the investigation of FET-based gas sensors’ sensitive material via measuring the work function variation induced by gas species adsorption. In this work an alternative technique to investigate gas sensitivity of materials suitable for implementation in DG-FET-based gas sensors, based on measurement of the surface charge induced by gas species adsorption is discussed. In order to increase the specific surface of the sensing electrode, a novel concept of functionalized gate surface texturing suitable for FET-based gas sensors are presented. It is based on the spray coating of a multi-walled-carbon nanotubes (MW-CNTs) suspension to deposit a MW-CNT porous network as a conducting frame for the sensing material. The main objective of this Ph.D. thesis can be divided into 4 parts: (1) modelling and simulation of a DG-SET and a FD-SOI MOSFET-based gas sensor response, and estimation of the sensitivity as well as the power consumption; (2) investigation of Pt sensitivity to hydrogen by surface charge measurement technique and development of the sensing electrode surface texturing process with CNT networks; (3) development and optimization of the DG-SET integration process in the BEOL of a CMOS substrate, and (4) FD-SOI MOSFET functionalization with Pt for H[subscript 2] sensing

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Temperature dependence of impurity resonances in cuprate superconductors

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Physics, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 66-73).In conventional superconductors the superconducting gap in the electronic excitation spectrum prevents scattering of low energy electrons. In high temperature superconductors (HTS) an additional gap, the pseudogap, develops well above the superconducting transition temperature Tc. The identity of this pseudogap and its relationship to high temperature superconductivity is one of the most interesting outstanding problems in condensed matter physics today. In this thesis I present a new avenue of investigating the pseudogap state, using scanning tunneling microscopy (STM) of resonances generated by single atom scatterers. First, I report that impurity resonance peaks, near zero bias in the excitation spectrum, continue to exist above the superconducting transition temperature and prove that the impurity resonance peak is unchanged through the superconducting transition. I also show that native impurity resonances coexist spatially with the superconducting gap at low temperatures. These findings demonstrate that properties of impurity resonances in HTS are not determined by the nature of the superconducting state, as previously suggested, but instead provide new insights into the pseudogap state. I will further provide preliminary results of doping dependence as a probe to study the pseudogap. In addition to these scientific results, I will also discuss advances I have made in STM instrumentation, from a novel technology to provide the excitation for the coarse approach mechanism of the STM to current amplifier circuits for faster spectroscopy measurements.by Kamalesh Chatterjee.Ph.D

Technology forecasting for space communication

A study was conducted to determine techniques for application to space communication. The subjects considered are as follows: (1) optical communication systems, (2) laser communications for data acquisition networks, (3) spacecraft data rate requirements, (4) telemetry, command, and data handling, (5) spacecraft tracking and data network antenna and preamplifier cost tradeoff study, and (6) spacecraft communication terminal evaluation

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

NASA SBIR abstracts of 1991 phase 1 projects

The objectives of 301 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1991 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 301, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1991 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included

Towards Single-Chip Nano-Systems

Important scientific discoveries are being propelled by the advent of nano-scale sensors that capture weak signals from their environment and pass them to complex instrumentation interface circuits for signal detection and processing. The highlight of this research is to investigate fabrication technologies to integrate such precision equipment with nano-sensors on a single complementary metal oxide semiconductor (CMOS) chip. In this context, several demonstration vehicles are proposed. First, an integration technology suitable for a fully integrated flexible microelectrode array has been proposed. A microelectrode array containing a single temperature sensor has been characterized and the versatility under dry/wet, and relaxed/strained conditions has been verified. On-chip instrumentation amplifier has been utilized to improve the temperature sensitivity of the device. While the flexibility of the array has been confirmed by laminating it on a fixed single cell, future experiments are necessary to confirm application of this device for live cell and tissue measurements. The proposed array can potentially attach itself to the pulsating surface of a single living cell or a network of cells to detect their vital signs