Principles, fundamentals, and applications of programmable integrated photonics

[EN] Programmable integrated photonics is an emerging new paradigm that aims at designing common integrated optical hardware resource configurations, capable of implementing an unconstrained variety of functionalities by suitable programming, following a parallel but not identical path to that of integrated electronics in the past two decades of the last century. Programmable integrated photonics is raising considerable interest, as it is driven by the surge of a considerable number of new applications in the fields of telecommunications, quantum information processing, sensing, and neurophotonics, calling for flexible, reconfigurable, low-cost, compact, and low-power-consuming devices that can cooperate with integrated electronic devices to overcome the limitation expected by the demise of Moore¿s Law. Integrated photonic devices exploiting full programmability are expected to scale from application-specific photonic chips (featuring a relatively low number of functionalities) up to very complex application-agnostic complex subsystems much in the same way as field programmable gate arrays and microprocessors operate in electronics. Two main differences need to be considered. First, as opposed to integrated electronics, programmable integrated photonics will carry analog operations over the signals to be processed. Second, the scale of integration density will be several orders of magnitude smaller due to the physical limitations imposed by the wavelength ratio of electrons and light wave photons. The success of programmable integrated photonics will depend on leveraging the properties of integrated photonic devices and, in particular, on research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated multiport interferometers and waveguide meshes provide regular and periodic geometries, formed by replicating unit elements and cells, respectively. In the case of waveguide meshes, the cells can take the form of a square, hexagon, or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach¿Zehnder interferometer or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we provide the basic foundations and principles behind the construction of these complex programmable circuits. We also review some practical aspects that limit the programming and scalability of programmable integrated photonics and provide an overview of some of the most salient applications demonstrated so far.European Research Council; Conselleria d'Educació, Investigació, Cultura i Esport; Ministerio de Ciencia, Innovación y Universidades; European Cooperation in Science and Technology; Horizon 2020 Framework Programme.Pérez-López, D.; Gasulla Mestre, I.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Principles, fundamentals, and applications of programmable integrated photonics. Advances in Optics and Photonics. 12(3):709-786. https://doi.org/10.1364/AOP.387155709786123Lyke, J. C., Christodoulou, C. G., Vera, G. A., & Edwards, A. H. (2015). An Introduction to Reconfigurable Systems. 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Energy efficiency is a critical challenge for today's integrated circuits, especially for high-end digital signal processing and communications that require both high throughput and low energy dissipation for extended battery life. Charge-recovery logic recovers and reuses charge using inductive elements and has the potential to achieve order-of-magnitude improvement in energy efficiency while maintaining high performance. However, the lack of large-scale high-speed silicon demonstrations and inductor area overheads are two major concerns. This dissertation focuses on scalable charge-recovery designs. We present a semi-automated design flow to enable the design of large-scale charge-recovery chips. We also present a new architecture that uses in-package inductors, eliminating the area overheads caused by the use of integrated inductors in high-performance charge-recovery chips. To demonstrate our semi-automated flow, which uses custom-designed standard-cell-like dynamic cells, we have designed a 576-bit charge-recovery low-density parity-check (LDPC) decoder chip. Functioning correctly at clock speeds above 1 GHz, this prototype is the first-ever demonstration of a GHz-speed charge-recovery chip of significant complexity. In terms of energy consumption, this chip improves over recent state-of-the-art LDPCs by at least 1.3 times with comparable or better area efficiency. To demonstrate our architecture for eliminating inductor overheads, we have designed a charge-recovery LDPC decoder chip with in-package inductors. This test-chip has been fabricated in a 65nm CMOS flip-chip process. A custom 6-layer FC-BGA package substrate has been designed with 16 inductors embedded in the fifth layer of the package substrate, yielding higher Q and significantly improving area efficiency and energy efficiency compared to their on-chip counterparts. From measurements, this chip achieves at least 2.3 times lower energy consumption with better area efficiency over state-of-the-art published designs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116653/1/terryou_1.pd

Design, Fabrication, and Characterization of Conjugated Polymeric Electrochemical Memristors as Neuromorphic/Integrated Circuits

Organic materials are promising candidates for future electronic devices compared to the complementing inorganic materials due to their ease of processability, use, and disposal, low cost of fabrication, energy efficiency, and flexible nature toward implementation as flexible and non-conformal devices.With that in mind, electrochemical materials have been widely demonstrated with commercial use as sensors, displays, and a variety of other electronic devices. As Moore\u27s law predicts the increase in the density of transistors on a chip, the requirement to create either smaller transistors or the replacement of the transistor device entirely is apparent. Memory resistors, coined ``memristor , are variable resistive tuning devices that are capable of information processing and data storage in one device. This work focuses on the embodiment of a non-volatile conjugated polymeric electrochemical memristor. Three-terminal memristive systems are fabricated and studied using various electrochemicals (a self-doped PEDOT derivative, a polypyrrole, and a dithienopyrrole derivative) and are tested for their electronic properties and biomimicking capabilities. Optical absorbance properties are studied in order to verify the electrochemical material\u27s redox tuning potential for their respective oxidized and reduced chemical forms. The three-terminal device employed a post-synaptic ``read\u27\u27 channel where conductivity of the electrochemical material was equated to synaptic weight and was electronically decoupled from the pre-synaptic programming electrode by means of a polymeric gel electrolyte. Basic electronic characteristics are exhibited for these three devices such as state stability and retention, non-volatile voltage-driven conductivity tuning, input parameter characteristic trends, and power consumption per input program. Biological synapses consume, on the order of, 1 - 100 fJ of energy per synaptic energy. The electrochemical materials used in this study, at their most optimized input parameters, were capable of demonstrating a 4.16 fJ/mm2 power consumption per input pulse and lead to a promising candidate for implementation as future artificial neural networks. Biological mimicry was displayed for these devices in the form of paired-pulse facilitation and paired-pulse depression, both a form of short term memory which observes the effect the timescale between two incoming inputs has on the change in the final output signal. Toward the indication for the replacement of transistors with three-terminal memristors, basic circuit operations are achieved and demonstrated for these devices. These operations include both Boolean and elementary algebra, key features that demonstrate data processing and storage in-memory where the physical states of the conjugated polymer film represent either logical statements or arithmetic counting variables. The Boolean algebra demonstrated the use of a single memristive device equal to a variety of single logic gates (AND, NAND, OR and NOR) where, by wiring several devices in series, more advanced combinational logic gates can be achieved. Furthermore, each device was capable of displaying elementary algebra for the basic arithmetic functions of addition, subtraction, multiplication, and division. In regards to thin film deposition techniques, the self-doped PEDOT device employed roll-to-roll gravure printing, a high speed and high resolution commercially used deposition technique. The polypyrrole device was fabricated implementing an in-situ polymerization technique, referred to as vapor phase polymerization, and demonstrated the use of this technique toward non-conformal devices. The dithienopyrrole derivative was polymerized through the same vapor phase polymerization technique as the polypyrrole and used in tandem with screen printing in order to construct the final device, including the oxidant film, the silver electrodes, and the polymeric gel electrolyte

Optimized Surface Code Communication in Superconducting Quantum Computers

Quantum computing (QC) is at the cusp of a revolution. Machines with 100 quantum bits (qubits) are anticipated to be operational by 2020 [googlemachine,gambetta2015building], and several-hundred-qubit machines are around the corner. Machines of this scale have the capacity to demonstrate quantum supremacy, the tipping point where QC is faster than the fastest classical alternative for a particular problem. Because error correction techniques will be central to QC and will be the most expensive component of quantum computation, choosing the lowest-overhead error correction scheme is critical to overall QC success. This paper evaluates two established quantum error correction codes---planar and double-defect surface codes---using a set of compilation, scheduling and network simulation tools. In considering scalable methods for optimizing both codes, we do so in the context of a full microarchitectural and compiler analysis. Contrary to previous predictions, we find that the simpler planar codes are sometimes more favorable for implementation on superconducting quantum computers, especially under conditions of high communication congestion.Comment: 14 pages, 9 figures, The 50th Annual IEEE/ACM International Symposium on Microarchitectur

RESISTIVE SWITCHING CHARACTERISTICS OF NANOSTRUCTURED AND SOLUTION-PROCESSED COMPLEX OXIDE ASSEMBLIES

Miniaturization of conventional nonvolatile (NVM) memory devices is rapidly approaching the physical limitations of the constituent materials. An emerging random access memory (RAM), nanoscale resistive RAM (RRAM), has the potential to replace conventional nonvolatile memory and could foster novel type of computing due to its fast switching speed, high scalability, and low power consumption. RRAM, or memristors, represent a class of two terminal devices comprising an insulating layer, such as a metal oxide, sandwiched between two terminal electrodes that exhibits two or more distinct resistance states that depend on the history of the applied bias. While the sudden resistance reduction into a conductive state in metal oxide insulators has been known for almost 50 years, the fundamental resistive switching mechanism is a complex phenomenon that is still long-debated, complex process. Further improvements to existing memristor performance require a complete understanding of memristive properties under various operation conditions. Additional technical issues also remain, such as the development of facile, low-cost fabrication methods as an alternative to expensive, ultra-high vacuum (UHV) deposition methods. This collection of work explores resistive switching within metal oxide-based memristive material assemblies by analyzing the fundamental physical insulating material properties. Chapter 3 aims to translate the utility and simplicity of the highly ordered anodic aluminum oxide (AAO) template structure to complex, yet more functional (memristive) materials. Functional oxides possessing ordered, scalable nanoporous arrays and nanocapacitor arrays over a large area is of interest to both the fields of next-generation electronics and energy storing/harvesting devices. Here their switching performance will be evaluated using conductive atomic force microscopy (C-AFM). Chapter 4 demonstrates a convective self-assembly fabrication method that effectively enables the synthesis of a low-cost solution processed memristor comprising binary oxide and perovskite ABO3 nanocrystals of varying diameter. Chapter 5 systematically compares the influence of inter-nanoparticle distance on the threshold switching SET voltage of hafnium oxide (HfO2) memristors. Utilizing shorter phosphonic acid ligands with higher binding affinity on the nanocrystal surface enabled a record-low SET voltage to be achieved. Chapter 6 extends the scope to the fine tuning of solution processed memristors with two types of perovskites nanocrystals. The primary advantage of nanocrystal memristors is the ability to draw from additional degrees of freedom by tuning the constituent nanocrystal material properties. Recent advancement of solution phase techniques enables a high degree of controllability over the nanocrystal size and structure. Thus, this work found in this dissertation aims to understand and decouple the effects of the geometric size and substitutional nanocrystal parameters on resistive switching

QUANTUM EVOLUTIONARY ALGORITHM FOR QUANTUM CIRCUIT SYNTHESIS

Quantum computing area has a lot research attention due to opportunities that possessing such device could provide. For example, quantum computers could deliver new insights to previously unsolvable problems. The reason for that is higher parallel capabilities of such devices. In addition, since quantum computers are naturally reversible, no heat dissipation occurs during computation [21]. This property could serve as a viable solution to the problem that computer chip production industry faces. Moreover, since the chip manufacturing industry reaches nanometer scale of size of elements, the effects that could cause unexpected information behavior in classical paradigm are part of the technology of quantum devices [31, 14]. Considering possible benefits that could be achieved by quantum computing devices, the new areas of Quantum Information Theory, Quantum Cryptography, Quantum Algorithms and Logic Design and many others emerged at the end of the twentieth century [31]. These areas are concentrating their efforts on solving problems of designing communication protocols, ensuring the security of the new systems, constructing appropriate algorithms. Computers that could be advancing in finding solutions in problems listed above require quantum circuits that have optimal structure and could implement error correction. This is the main motivation for this thesis work to explore the problem of circuit design. The approach that we investigate is circuit construction by the means of Quantum Evolutionary Algorithms. We propose a version of an algorithm that accounts with specificity and constraints of quantum paradigm. We use its Graphic Processing Unit (GPU) accelerated classical implementation to evaluate the behavior and performance of the proposed algorithm. Later we discuss additional complexity introduced by accounting with these constraints. We support our ideas with results of synthesis of small circuits and compare the performance with classical genetic algorithm on similar task