A novel triangular wave quadrature oscillator without passive components for sinusoidal pulse width modulation DC-AC power conversion

In this study, a low-cost quadrature triangle oscillator using a voltage-controlled closed-loop dual operational amplifier (Op-Amp) architecture is proposed. Unlike other typical designs, this oscillator does not require any passive components. The use of an Op-Amp-based circuit is attractive for a triangle oscillator because it is more cost-effective than a microcontroller-based solution. This is especially true for sinusoidal pulse width modulation (SPWM) DC-AC power conversion applications. The slew-rate restriction of an Op-Amp is a useful characteristic for producing a triangle waveform when seen from the perspective of wave shaping techniques. The MC4558 and the JRC4558D are two examples of dual Op-Amps that are evaluated, contrasted, and described in this article. At supply voltages of +7 V and -7 V, the suggested quadrature triangle oscillator that uses Op-Amps MC4558 and JRC4558D has the same oscillation frequency, which is 63 kHz, as demonstrated by simulation and experimental data. The frequency stability is estimated to be around 0.23%. In addition, the findings from the experiment demonstrate that the proposed oscillator is a practical solution for the SPWM DC-AC power conversion application

Differential Difference Current Conveyor (DDCC) Based Schmitt Trigger Circuit & Its Application

A new voltage mode Schmitt trigger and its application using Differential Difference Current Conveyor (DDCC) is presented in this paper. The proposed circuit has a single DDCC block & two passive components. This circuit does not have any matching conditions. Here two passive components are used and one of them is grounded .The proposed circuit is simulated on SPICE platfor

Circuits for Analog Signal Processing Employing Unconventional Active Elements

Disertační práce se zabývá zaváděním nových struktur moderních aktivních prvků pracujících v napěťovém, proudovém a smíšeném režimu. Funkčnost a chování těchto prvků byly ověřeny prostřednictvím SPICE simulací. V této práci je zahrnuta řada simulací, které dokazují přesnost a dobré vlastnosti těchto prvků, přičemž velký důraz byl kladen na to, aby tyto prvky byly schopny pracovat při nízkém napájecím napětí, jelikož poptávka po přenosných elektronických zařízeních a implantabilních zdravotnických přístrojích stále roste. Tyto přístroje jsou napájeny bateriemi a k tomu, aby byla prodloužena jejich životnost, trend navrhování analogových obvodů směřuje k stále většímu snižování spotřeby a napájecího napětí. Hlavním přínosem této práce je návrh nových CMOS struktur: CCII (Current Conveyor Second Generation) na základě BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na základě FG, transkonduktor na základě nové techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na základě GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na základě GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na základě BD. Dále je uvedeno několik zajímavých aplikací užívajících výše jmenované prvky. Získané výsledky simulací odpovídají teoretickým předpokladům.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.

A Flexible RFIC Architecture for High-Sensitivity Reception and Compressed-Sampling Wideband Detection

Compressed sensing (CS) is a new signal processing approach that has disrupted the Shannon-Nyquist limit based design methodology and has opened promising avenues for building energy-efficient radio frequency integrated circuits (RFICs) for detecting and estimating particular classes (i.e. sparse) of signals. Whether in application domains where naturally occurring signals are sparse or where representations of signals subject to the fidelity limits or configuration settings of the radio equipment are often found to be sparse, the emergence of CS has forced us to re-imagine the radio receiver. While realizing some of the potential benefits promised by theory, CS-RFIC architectures proposed in earlier research were not particularly suitable for mass-market applications. This thesis demonstrates how to take a new signal processing technique all the way to the hardware level. So far, the main focus in literature has been how CS offers a significant advantage for signal processing. This work will show how CS techniques drive novel architectures down to the integrated circuit level. This requires close collaboration between communication system developers, integrated circuit designers and signal processing experts. The trans-disciplinary approach presented here has led to the unification of CS-inspired architectures for wideband signal detection with robust, legacy architectures for high-sensitivity signal reception. The result is a functionally flexible and rapidly reconfigurable CMOS RFIC compactly implemented on silicon with the potential to achieve the cost, size and power targets in mass-market applications. While the focus of this thesis is RF signal finding and reception in frequency, the CS-based RFIC design approach presented here is applicable to a wide range of other applications like direction-of-arrival and range finding. We begin by developing a signal-model driven approach for optimizing the performance of CS RF frontends (RFFEs). We consider sparse multiband signals with supports contained within a frequency span extending from fMIN to fMAX. The resulting quadrature analog-to-information converter (QAIC) is a flexible-bandwidth, blind sub-Nyquist sampling architecture optimized for energy consumption and sensitivity performance. The QAIC addresses key drawbacks of earlier CS RFFE architectures like the modulated wideband converter (MWC) that implement frequency spans extending from 0 to fMAX. While these earlier architectures, a direct implementation of CS signal processing theory, have several beneficial properties, the true cost of their proposed analog frontend significantly diminishes the sensitivity performance and energy savings that CS methods have the potential to deliver. They use periodic pseudo-random bit sequence (PRBS) generators where the clock frequency fPRBS scales up with the maximum signal frequency fMAX. In contrast, fPRBS in the QAIC RFFE scales up with the instantaneous bandwidth IBW, where IBW = ( fMAX − fMIN ). This results in significant performance advantages in terms of energy consumption and sensitivity performance. The QAIC uncouples fPRBS from fMAX by performing wideband quadrature downconversion ahead of analog mixing with PRBSs at an intermediate frequency (IF). However, the dual heterodyne architecture of the QAIC suffers from spurious responses at IF caused by gain and phase imbalance in its wideband downconverter. We then show how the direct RF-to-information converter (DRF2IC) compactly adds CS wideband detection to a direct conversion frequency-translational noise-cancelling (FTNC) receiver by introducing pseudo-random modulation of the local oscillator (LO) signals and by consolidating multiple CS measurements into one hardware branch. The DRF2IC inherits benefits of the FTNC receiver in signal reception mode. In CS wideband detection mode, the DRF2IC inherits key advantages from both the earlier lowpass CS architectures and the QAIC while avoiding the drawbacks of both. It uncouples fPRBS from fMAX in contrast with the MWC. In contrast with the QAIC, the DRF2IC employs a direct conversion RF chain with narrow bandwidth analog components at baseband thereby avoiding frequency-dependent gain and phase imbalance. The DRF2IC chip occupies 0.56mm2 area in 65nm CMOS. In reception mode, it consumes 46.5mW from 1.15V and delivers 40MHz RF bandwidth, 41.5dB conversion gain, 3.6dB noise figure (NF) and -2dBm blocker 1dB compression point (B1dB). In CS wideband detection mode, 66dB operational dynamic range, 40dB instantaneous dynamic range and 1.43GHz instantaneous bandwidth are demonstrated and 6 interferers each 10MHz wide scattered over a 1.27GHz span are detected in 1.2us consuming 58.5mW

Analog Reconfigurable Circuits

The aim of this paper is to present an overview of a new branch of analog electronics represented by analog reconfigurable circuits. The reconfiguration of analog circuits has been known and used since the beginnings of electronics, but the universal reconfigurable circuits called Field Programmable Analog Arrays (FPAA) have been developed over the last two decades. This paper presents the classification of analog circuit reconfiguration, examples of FPAA solutions obtained as academic projects and commercially available ones, as well as some application examples of the dynamic reconfiguration of FPAA.

Electronically Tunable Oscillator Utilizing Reinforced Controllable Parameters

This paper presents a novel solution of an oscillator with electronically adjustable oscillation condition (CO) and frequency of oscillations (FO). Oscillation condition is controlled by current gain and frequency of oscillations is adjustable by transconductance and intrinsic resistance of used active elements. Both CO and FO are mutually independent. Moreover, special feature of CO allows boosting parameter driving FO (transconductance) and then shifting the whole FO range to higher bands. It allows to keep values of passive elements (capacitors especially) in satisfactory range even for higher value of FO. Simulations in PSpice confirms this hypothesis

New Electronic Interface Circuits for Humidity Measurement Based on the Current Processing Technique

The paper describes a new electronic conditioning circuit based on the current-processing technique for accurate and reliable humidity measurement, without post-processing requirements. Pseudobrookite nanocrystalline (Fe2TiO5) thick film was used as capacitive humidity transducer in the proposed design. The interface integrated circuit was realized in TSMC 0.18 mu m CMOS technology, but commercial devices were used for practical realization. The sensing principle of the sensor was obtained by converting the information on environment humidity into a frequency variable square-wave electric current signal. The proposed solution features high linearity, insensitivity to temperature, as well as low power consumption. The sensor has a linear function with relative humidity in the range of Relative Humidity (RH) 30-90 %, error below 1.5 %, and sensitivity 8.3 x 10(14) Hz/F evaluated over the full range of changes. A fast recovery without the need of any refreshing methods was observed with a change in RH. The total power dissipation of readout circuitry was 1 mW

Design of Signal Generators Using Active Elements Developed in I3T25 CMOS Technology Single IC Package for Illuminance to Frequency Conversion

This paper presents a compact and simple design of adjustable triangular and square wave functional generators employing fundamental cells fabricated on a single integrated circuit (IC) package. Two solutions have electronically tunable repeating frequency. The linear adjustability of repeating frequency was verified in the range between 17 and 264 kHz. The main benefits of the proposed generator are the follows: A simple adjustment of the repeating frequency by DC bias current, Schmitt trigger (threshold voltages) setting by DC driving voltage, and output levels in hundreds of mV when the complementary metal-oxide semiconductor (CMOS) process with limited supply voltage levels is used. These generators are suitable to provide a simple conversion of illuminance to frequency of oscillation that can be employed for illuminance measurement and sensing in the agriculture applications. Experimental measurements proved that the proposed concept is usable for sensing of illuminance in the range from 1 up to 500 lx. The change of illuminance within this range causes driving of bias current between 21 and 52 mu A that adjusts repeating frequency between 70 and 154 kHz with an error up to 10% between the expected and real cases

Arbitrarily Tunable Phase Shift in Low-Frequency Multiphase Oscillator

A special electronically tunable multiphase oscillator with arbitrarily and continuously adjustable phase shifts is introduced. Our design assumes to set the phase around the asymptotical limit of 180.. These features cannot be easily achieved in a standard way, i.e., any simple single-phase oscillator supplemented by a first-order adjustable all-pass (AP) section (shifter). The proposed design uses an electronically linearly tunable quadrature oscillator with a frequency range from 0.98 up to 12.54 kHz. It also offers multiples of 45. as the initial setting of the phase shift tuning region. The example of operation shows the adjustment of the phase shift at a specific frequency (10 kHz) within the range of +/- 45 degrees. and around -180 degrees, -135 degrees, and -90 degrees. This variability is not available in standard cases without the use of several AP sections. The current value of the phase shift of the presented oscillator is electronically controlled and does not influence the oscillation frequency and condition of oscillation. Output levels of produced signals are not influenced by this tuning process and are in the range of several hundreds of mV. Two applications of the oscillator are proposed. The first one focuses on low-bitrate modulation systems [phase shift keying (PSK)] while in the second one, our circuit represents a source of phase-adjustable signals in acoustic experiments. Discrete passive elements and active devices (special multipliers having current output terminals, unity-gain differential voltage buffers) fabricated in 0.35 mu m I3T25 ON Semiconductor 3.3 V CMOS process are used in experimental verification

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development