271 research outputs found

    A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

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    © 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

    A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

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    © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

    Towards a Universal Multi-Standard RF Receiver

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    Future wireless communication market calls for the need of an extreme compact wireless device that can easily access to all the available services at any time and at any location with minimum power consumption and cost. The key is to find a multi-standard wireless receiver that can cover all the service specifications while keeping redundant components to minimum. Reconfigurable concept is right fit the need. In this thesis, a fully integrated universal multi-standard receiver using low-cost CMOS technology has been proposed based on the survey for different wireless receiver specifications and optimum architectures. Tunable receiver building blocks such as filters, LNAs, Mixers, VCOs, gain blocks are the main factor to approach this novel receiver. In order to realize frequency agility, low cost as well as low power consumption, a good switch is a must. In this thesis, MEMS switches are preferred rather than active switches or active tuning elements based on their performance comparisons. In the feasibility study, as an example, first, a reconfigurable LNA and a reconfigurable oscillator using hard wires as switches have been developed, and then a LNA and an oscillator have been designed using a MEMS switch. The effect of hard-wire connection and MEMS to the circuits has been evaluated. No performance degradation has been found when using hard-wire connections, while some has been observed when using MEMS. However, MEMS could be integrated with other circuits on the same die if it could be built on low resistive silicon substrate without performance degradation

    Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

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    The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA) based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends

    Analysis of Impact of Transformer Coupled Input Matching on Concurrent Dual-Band Low Noise Amplifier

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    Emerging advancements in telecommunication system need robust radio devices which can capable of working multiple frequency bands seamlessly. In any Radio Frequency (RF) receiver architecture, Low Noise Amplifier (LNA) is the mandatory front-end part in which takes place in between antenna and mixer. To support multiple frequency bands with single hardware, concurrent LNA is the more preferred topologies among others. As LNA is the very front end level of receiver, Input matching, Noise Figure (NF) and gain are the major performance parameters to be concerned. In this work, the impact of transformer coupled input matching on concurrent dual-band LNA is analyzed and verified. A concurrent LNA with concurrent matching without transformer coupling is used for comparison. A transformer coupled input matching is proposed for tunable concurrent dual-band LNA. All the circuits are implemented in UMC 180nm CMOS technology, and simulated using Cadence SpectreRF simulation tool

    Design Of Integrated Reconfigurable Rfcmos Low-Noise Amplifiers For Cellular And Wireless Systems

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    Perkembangan ekstensif dalam dunia komunikasi mudah alih telah menghasilkan cabaran baharu kepada “transceiver” tanpa wayar disebabkan keperluan beroperasi pada pelbagai jalur frekuensi dan piawaian. Perkembangan ini menggalakkan penyelidikan mengenai LNA frekuensi konfigurasi semula berbilang-jalur berbilangpiawaian menggantikan berbilang LNA jalur-tunggal yang selari. Ini dapat mengurangkan keluasan “die” dan lesapan kuasa yang memenuhi keupayaan mudah alih dan kesepaduan yang tinggi. Dalam projek ini, tiga teknik frekuensi konfigurasi semula diperkenalkan bagi mereka bentuk LNA kaskod induktif-ternyahjana dwi-jalur yang berkeupayaan menghasilkan padanan masukan dan hingar serentak walaupun terdapat kekangan kuasa. Semua reka bentuk dilaksanakan menggunakan teknologi 0.13-μm RFCMOS beroperasi pada 900-MHz dan 1900-MHz GSM serta 2450-MHz dan 3650-MHz WLAN. Di samping itu, dua LNA jalur-tunggal telah dibangunkan untuk beroperasi pada 900-MHz dan 2450-MHz bagi tujuan perbandingan. Teknik yang diperkenalkan ialah hibrid teknik kapasitan tersuis, hibrid teknik lebartransistor/ transkonduktans/kapasitan-Miller tersuis dan teknik aruhan boleh ubah berasaskan transformer. Teknik-teknik ini mengurangkan keluasan kapasitor, dan menghasilkan prestasi hingar dan gandaan yang lebih baik bagi kedua-dua jalur di samping mengekalkan pemadanan hingar dan masukan serentak berbanding dengan teknik konfigurasi semula konvensional. Persamaan dihasilkan untuk reka bentuk awal LNA bagi menilai teknik sebelum pelaksanaan. Keputusan simulasi pasca-bentangan dibandingkan dengan keputusan pengukuran bagi penilaian dan pengesahan. Semua reka bentuk LNA dwi-jalur mencapai kelebihan yang dipunyai oleh LNA jalur-tunggal jalur-sempit melalui prestasi mereka yang tinggi di samping mencapai juga kelebihan LNA jalur-lebar disebabkan liputan pelbagai-jalur pelbagai-piawaian. Semua reka bentuk berupaya mencapai angka hingar di antara 1.55 ke 3.97 dB, dengan S11 kurang dari -10 dB, di samping gandaan melebihi 13.4 dB, pada lesapan kuasa di bawah 10 mW bagi semua jalur operasi. Metrik kelelurusan, IIP3 dan P1dB, adalah lebih baik dari masing-masing, -8 dBm dan -21 dBm. Lebar jalur bagi semua LNA adalah cukup untuk meliputi semua jalur piawaian yang dikehendaki. Prestasi ini menunjukkan bahawa semua reka bentuk berupaya untuk memenuhi spesifikasi sasaran bagi jalur 900-MHz, 1900-MHz, 2450-MHz dan 3650-MHz. Sebagai tambahan kepada semua pencapaian ini, satu kaedah baharu berdasarkan analisa elektromagnetik telah dibangunkan yang boleh menggantikan simulasi pasca-bentangan (PLS) menggunakan ekstrak parasitik RC konvensional. Kaedah elektromagnet ini dapat menganggarkan dengan lebih tepat anjakan frekuensi yang dilihat daripada keputusan pengukuran berbanding dengan PLS dengan ekstrak parasitik RC konvensional. Di samping itu, kaedah ini juga boleh membantu pereka bentuk untuk diagnos dengan lebih tepat reka bentuk LNA bersepadu-penuh tanpa komponen luar-cip sebelum rekabentuk itu difabrikasi. ________________________________________________________________________________________________________________________ The extensive growth in worldwide mobile communications has introduced new challenges to wireless transceivers as they need to operate at a variety of frequency bands and standards. This encourages researches on multi-band multi-standard frequency-reconfigurable LNAs as an option to multiple parallel single-band LNAs. This reduces the die area and power consumption and provides higher mobility and integration. In this work, three frequency-reconfigurable techniques were introduced to design dual-band inductively-degenerated cascode LNAs with power-constrained simultaneous noise and input matching capability. The designs were implemented in 0.13-μm RFCMOS technology to operate at 900-MHz and, 1900-MHz GSM, and 2450-MHz and 3650-MHz WLAN standard bands. In addition to dual-band LNAs, two single band LNAs were developed to operate at 900-MHz and 2450-MHz for comparison purpose. The techniques introduced were hybrid of switched capacitances technique, hybrid of switched transistor-width/transconductance/Miller-capacitance technique and transformer-based variable inductance technique. The techniques introduced less capacitor area, better noise and gain performances for both bands and preserved simultaneous noise and input matching compared to conventional reconfigurable techniques. Equations were developed for initial LNA designs to evaluate the techniques before implementation. The post-layout simulation results were compared to measurement results for evaluation and verification. The measured results satisfied all objectives of this work. The dual-band LNA designs showed advantages of a single-band narrow-band LNA because of its high performance together with the advantage of a wideband LNA because of its multi-band multistandard coverage. For all operating bands, all designs could achieve noise figure between 1.55 and 3.97 dB with S11 less than -10 dB as well as gains more than 13.4 dB while the power consumption were lower than 10 mW. IIP3 and P1dB as linearity metrics were better than -8 dBm and -21 dBm, respectively. The bandwidth for all LNAs were sufficient to cover the required bands for desired standards. These performances show that all design are able to meet the targeted specification for 900- MHz, 1900-MHz, 2450-MHz and 3650-MHz bands. In addition to these findings, a new method based on electromagnetic analysis was developed that can replace the conventional post-layout simulation with RC parasitic extraction. The electromagnetic method predicted the frequency shift observed in the measurement more accurately than the conventional PLS with RC parasitic extraction. Also, using this method, designers are able to diagnose the fully-integrated LNA designs with no off-chip component before fabrication more precisely

    Analysis and Design of Wideband Low Noise Amplifier with Digital Control

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    The design issues in designing low noise amplifier (LNA) for Software-Defined-Radio (SDR) are reviewed. An inductor-less wideband low noise amplifier aiming at low frequency band (0.2-2GHz) for Software-Defined-Radio is presented. Shunt-shunt LNA with active feedback is used as the first stage which is carefully optimized for low noise and wide band applications. A digitally controlled second stage is employed to provide an additional 12dB gain control. A novel method is proposed to bypass the first stage without degrading input matching. This LNA is fabricated in a standard 0.18 um CMOS technology. The measurement result shows the proposed LNA has a gain range of 6dB-18dB at high gain mode and -12dB-0dB at low gain mode, as well as a –3dB bandwidth of 2GHz. The noise figure (NF) is 3.5-4.5dB in the high gain setting mode. It consumes 20mW from a 1.8V supply
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