Parallel implementation of a virtual reality system on a transputer architecture

A Virtual Reality is a computer model of an environment, actual or imagined, presented to a user in as realistic a fashion as possible. Stereo goggles may be used to provide the user with a view of the modelled environment from within the environment, while a data-glove is used to interact with the environment. To simulate reality on a computer, the machine has to produce realistic images rapidly. Such a requirement usually necessitates expensive equipment. This thesis presents an implementation of a virtual reality system on a transputer architecture. The system is general, and is intended to provide support for the development of various virtual environments. The three main components of the system are the output device drivers, the input device drivers, and the virtual world kernel. This last component is responsible for the simulation of the virtual world. The rendering system is described in detail. Various methods for implementing the components of the graphics pipeline are discussed. These are then generalised to make use of the facilities provided by the transputer processor for parallel processing. A number of different decomposition techniques are implemented and compared. The emphasis in this section is on the speed at which the world can be rendered, and the interaction latency involved. In the best case, where almost linear speedup is obtained, a world containing over 250 polygons is rendered at 32 frames/second. The bandwidth of the transputer links is the major factor limiting speedup. A description is given of an input device driver which makes use of a powerglove. Techniques for overcoming the limitations of this device, and for interacting with the virtual world, are discussed. The virtual world kernel is designed to make extensive use of the parallel processing facilities provided by transputers. It is capable of providing support for mUltiple worlds concurrently, and for multiple users interacting with these worlds. Two applications are described that were successfully implemented using this system. The design of the system is compared with other recently developed virtual reality systems. Features that are common or advantageous in each of the systems are discussed. The system described in this thesis compares favourably, particularly in its use of parallel processors.KMBT_22

An Embedded Garbage Collection Module with Support for Multiple Mutators and Weak References

This report details the design of a garbage collection (GC) module, which introduces modern GC features to the domain of embedded implementations. The described design supports weak references and feeds reference queues. Its architecture allows multiple concurrent application cores operating as mutators on the shared memory managed by the GC module. The garbage collection is exact and fully concurrent so as to enable the uninterrupted computational progress of the mutators. It combines a distributed root marking with a centralized heap scan of the managed memory. It features a novel mark-and-copy GC strategy on a segmented memory, which thereby overcomes both the tremendous space overhead of two-space copying and the compaction race of mark-and-compact approaches. The proposed GC architecture has been practically implemented and proven using the embedded bytecode processor SHAP as a sample testbed. The synthesis results for settings up to three SHAP mutator cores are given and online functional measurements are presented. Basic performance dependencies on the system configuration are evaluated

Interconnect yield analysis and fault tolerance for field programmable gate arrays

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Architecture FPGA améliorée et flot de conception pour une reconfiguration matérielle en ligne efficace

The self-reconfiguration capabilities of modern FPGA architectures pave the way for dynamic applications able to adapt to transient events. The CAD flows of modern architectures are nowadays mature but limited by the constraints induced by the complexity of FPGA circuits. In this thesis, multiple contributions are developed to propose an FPGA architecture supporting the dynamic placement of hardware tasks. First, an intermediate representation of these tasks configuration data, independent from their final position, is presented. This representation allows to compress the task data up to 11x with regard to its conventional raw counterpart. An accompanying CAD flow, based on state-of-the-art tools, is proposed to generate relocatable tasks from a high-level description. Then, the online behavior of this mechanism is studied. Two algorithms allowing to decode and create in real-time the conventional bit-stream are described. In addition, an enhancement of the FPGA interconnection network is proposedto increase the placement flexibility of heterogeneous tasks, at the cost of a 10% increase in average of the critical path delay. Eventually, a configurable substitute to the configuration memory found in FPGAs is studied to ease their partial reconfiguration.Les capacités d'auto-reconfiguration des architectures FPGA modernes ouvrent la voie à des applications dynamiques capables d'adapter leur fonctionnement pour répondre à des évènements ponctuels. Les flots de reconfiguration des architectures commerciales sont aujourd'hui aboutis mais limités par des contraintes inhérentes à la complexité de ces circuits. Dans cette thèse, plusieurs contributions sont avancées afin de proposer une architecture FPGA reconfigurable permettant le placement dynamique de tâches matérielles. Dans un premier temps, une représentation intermédiaire des données de configuration de ces tâches, indépendante de leur positionnement final, est présentée. Cette représentation permet notamment d'atteindre des taux de compression allant jusqu'à 11x par rapport à la représentation brute d'une tâche. Un flot de conception basé sur des outils de l'état de l'art accompagne cette représentation et génère des tâches relogeables à partir d'une description haut-niveau. Ensuite, le comportement en ligne de ce mécanisme est étudié. Deux algorithmes permettant le décodage de ces tâches et la génération en temps-réel des données de configuration propres à l'architectures son décrits. Par ailleurs, une amélioration du réseau d'interconnexion d'une architecture FPGA est proposée pour accroître la flexibilité du placement de tâches hétérogènes, avec une augmentation de 10% en moyenne du délai du chemin critique. Enfin, une alternative programmable aux mémoires de configuration de ces circuits est étudiée pour faciliter leur reconfiguration partielle

Comparative study of networks using packet and circuit switching within a single network

During the last couple of years, in addition to voice, other types of communications network services are becoming increasingly important. These are interactive data, facsimile, slow scan image, and bulk data. Typically, these services are delivered by separate networks using various kinds of switching technology, such as packet, circuit, or message switching. Recently, much of the focus has been on the integration of all types of communication services within the same switch or network, especially within the telephony and business industry. Integration of the communication services is being realized by integrating packet and circuit switching within the same switch or network. The overall goal of this thesis is to present the key aspects of the integration of circuit and packet switching within the same switch/network

Pursuing cost-effective secure network micro-segmentation

Traditional network segmentation allows discrete trust levels to be defined for different network segments, using physical firewalls or routers that control north-south traffic flowing between different interfaces. This technique reduces the attack surface area should an attacker breach one of the perimeter defences. However, east-west traffic flowing between endpoints within the same network segment does not pass through a firewall, and an attacker may be able to move laterally between endpoints within that segment. Network micro-segmentation was designed to address the challenge of controlling east-west traffic, and various solutions have been released with differing levels of capabilities and feature sets. These approaches range from simple network switch Access Control List based segmentation to complex hypervisor based software-defined security segments defined down to the individual workload, container or process level, and enforced via policy based security controls for each segment. Several commercial solutions for network micro-segmentation exist, but these are primarily focused on physical and cloud data centres, and are often accompanied by significant capital outlay and resource requirements. Given these constraints, this research determines whether existing tools provided with operating systems can be re-purposed to implement micro-segmentation and restrict east-west traffic within one or more network segments for a small-to-medium sized corporate network. To this end, a proof-of-concept lab environment was built with a heterogeneous mix of Windows and Linux virtual servers and workstations deployed in an Active Directory domain. The use of Group Policy Objects to deploy IPsec Server and Domain Isolation for controlling traffic between endpoints is examined, in conjunction with IPsec Authenticated Header and Encapsulating Security Payload modes as an additional layer of security. The outcome of the research shows that revisiting existing tools can enable organisations to implement an additional, cost-effective secure layer of defence in their network

A Self-Configuring 3-D Body Scanner

A flexible, self-configuring body scanner is described that is capable of capturing and merging range data from multiple views into a single coordinate system without the use of registration. The scanner uses two disconnected frames with embedded lights to merge the coordinate systems of multiple cameras. The frame also serves in finding the laser plane as the lasers are swept over the surface from multiple locations. Both hardware and software details are presented as well as techniques for automating most aspects of the scanner. A new implicit surface implementation is also described for processing and triangulating the resulting point clouds along with the design and use of measurement tools for analyzing the completed scan

Nanometer-precision electron-beam lithography with applications in integrated optics

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 179-185).Scanning electron-beam lithography (SEBL) provides sub-10-nm resolution and arbitrary-pattern generation; however, SEBL's pattern-placement accuracy remains inadequate for future integrated-circuits and integrated-optical devices. Environmental disturbances, system imperfections, charging, and a variety of other factors contribute to pattern-placement inaccuracy. To overcome these limitations, spatial-phase locked electron-beam lithography (SPLEBL) monitors the beam location with respect to a reference grid on the substrate. Phase detection of the periodic grid signal provides feedback control of the beam position to within a fraction of the period. Using this technique we exposed patterns globally locked to a fiducial grid and reduced local field-stitching errors to a < 1.3 nm. Spatial-phase locking is particularly important for integrated-optical devices that require pattern-placement accuracy within a fraction of the wavelength of light. As an example, Bragg-grating based optical filters were fabricated in silicon-on-insulator waveguides using SPLEBL. The filters were designed to reflect a narrow-range of wavelengths within the communications band near 1550-nm. We patterned the devices in a single lithography step by placing the gratings in the waveguide sidewalls. This design allows apodization of the filter response by lithographically varying the grating depth. Measured transmission spectra show greatly reduced sidelobe levels for apodized devices compared to devices with uniform gratings.by Jeffrey Todd Hastings.Ph.D