Energy efficient core designs for upcoming process technologies

Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are being actively explored to extend the march in increasing the computational power and efficiency. It is essential for computer architects to understand the opportunities and challenges in utilizing the upcoming process technology trends in order to design the most efficient processors. In this work, we consider three process technology trends and propose core designs that are best suited for each of the technologies. The process technologies are expected to be viable over a span of timelines. We first consider the most popular method currently available to improve the energy efficiency, i.e. by lowering the operating voltage. We make key observations regarding the limiting factors in scaling down the operating voltage for general purpose high performance processors. Later, we propose our novel core design, ScalCore, one that can work in high performance mode at nominal Vdd, and in a very energy-efficient mode at low Vdd. The resulting core design can operate at much lower voltages providing higher parallel performance while consuming lower energy. While lowering Vdd improves the energy efficiency, CMOS devices are fundamentally limited in their low voltage operation. Therefore, we next consider an upcoming device technology -- Tunneling Field-Effect Transistors (TFETs), that is expected to supplement CMOS device technology in the near future. TFETs can attain much higher energy efficiency than CMOS at low voltages. However, their performance saturates at high voltages and, therefore, cannot entirely replace CMOS when high performance is needed. Ideally, we desire a core that is as energy-efficient as TFET and provides as much performance as CMOS. To reach this goal, we characterize the TFET device behavior for core design and judiciously integrate TFET units, CMOS units in a single core. The resulting core, called HetCore, can provide very high energy efficiency while limiting the slowdown when compared to a CMOS core. Finally, we analyze Monolithic 3D (M3D) integration technology that is widely considered to be the only way to integrate more transistors on a chip. We present the first analysis of the architectural implications of using M3D for core design and show how to partition the core across different layers. We also address one of the key challenges in realizing the technology, namely, the top layer performance degradation. We propose a critical path based partitioning for logic stages and asymmetric bit/port partitioning for storage stages. The result is a core that performs nearly as well as a core without any top layer slowdown. When compared to a 2D baseline design, an M3D core not only provides much higher performance, it also reduces the energy consumption at the same time. In summary, this thesis addresses one of the fundamental challenges in computer architecture -- overcoming the fact that CMOS is not scaling anymore. As we increase the computing power on a single chip, our ability to power the entire chip keeps decreasing. This thesis proposes three solutions aimed at solving this problem over different timelines. Across all our solutions, we improve energy efficiency without compromising the performance of the core. As a result, we are able to operate twice as many cores with in the same power budget as regular cores, significantly alleviating the problem of dark silicon

Index to NASA tech briefs, 1971

The entries are listed by category, subject, author, originating source, source number/Tech Brief number, and Tech Brief number/source number. There are 528 entries

Feasibility study for a numerical aerodynamic simulation facility. Volume 1

A Numerical Aerodynamic Simulation Facility (NASF) was designed for the simulation of fluid flow around three-dimensional bodies, both in wind tunnel environments and in free space. The application of numerical simulation to this field of endeavor promised to yield economies in aerodynamic and aircraft body designs. A model for a NASF/FMP (Flow Model Processor) ensemble using a possible approach to meeting NASF goals is presented. The computer hardware and software are presented, along with the entire design and performance analysis and evaluation

Cumulative Index to NASA Tech Briefs, 1963 - 1966

Cumulative index of NASA Tech Briefs dealing with electrical and electronic, physical science and energy sources, materials and chemistry, life science, and mechanical innovation

Cumulative index to NASA Tech Briefs, 1963-1967

Cumulative index to NASA survey on technology utilization of aerospace research outpu

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 04)

For abstract, see N74-20609

NASA Tech Briefs Index, 1978

Approximately 601 announcements of new technology derived from the research and development activities of the National Aeronautics and Space Administration are presented. Emphasis is placed on information considered likely to be transferrable across industrial, regional, or disciplinary lines. Subject matter covered includes: electronic components and circuits; electron systems; physical sciences; materials; life sciences; mechanics; machinery; fabrication technology; and mathematics and information sciences

Transparent mode flip-flops for collapsible pipelines

Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70 % of the dynamic power in modern high performance microprocessors. Previous collapsible pipeline proposals either rely on single phase clocking (by forcing latches into transparent state) or do not discuss the mechanisms by which stages are merged. In this work two flip-flop designs featuring an additional transparent state suitable for collapsing stages are presented. Transparency is achieved either by decoupling the master and slave clocks to keep both latches transparent, or by using a bypass mux that routes around the flip-flop. Both of these designs are evaluated in the context of transparently gated pipelines, an ad-hoc collapsible pipelining technique. Detailed analysis shows that the decoupled clock flipflop is the most attractive in terms of energy and delay. 1

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 06)

For abstract, see N75-20149

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 12)

For abstract, see N78-27983