Low-Power Design of Digital VLSI Circuits around the Point of First Failure

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling proved to effectively reduce the energy consumption of digital circuits, additional energy savings are still required for a longer battery life. One of the main limitations of essentially any low-energy technique is the potential degradation of the quality of service (QoS). Thus, a thorough understanding of how circuits behave when operated around the point of first failure (PoFF) is key for the effective application of conventional energy-efficient methods as well as for the development of future low-energy techniques. In this thesis, a variety of circuits, techniques, and tools is described to reduce the energy consumption in digital systems when operated either in the safe and conservative exact region, close to the PoFF, or even inside the inexact region. A straightforward approach to reduce the power consumed by clock distribution while safely operating in the exact region is dual-edge-triggered (DET) clocking. However, the DET approach is rarely taken, primarily due to the perceived complexity of its integration. In this thesis, a fully automated design flow is introduced for applying DET clocking to a conventional single-edge-triggered (SET) design. In addition, the first static true-single-phase-clock DET flip-flop (DET-FF) that completely avoids clock-overlap hazards of DET registers is proposed. Even though the correct timing of synchronous circuits is ensured in worst-case conditions, the critical path might not always be excited. Thus, dynamic clock adjustment (DCA) has been proposed to trim any available dynamic timing margin by changing the operating clock frequency at runtime. This thesis describes a dynamically-adjustable clock generator (DCG) capable of modifying the period of the produced clock signal on a cycle-by-cycle basis that enables the DCA technique. In addition, a timing-monitoring sequential (TMS) that detects input transitions on either one of the clock phases to enable the selection of the best timing-monitoring strategy at runtime is proposed. Energy-quality scaling techniques aimat trading lower energy consumption for a small degradation on the QoS whenever approximations can be tolerated. In this thesis, a low-power methodology for the perturbation of baseline coefficients in reconfigurable finite impulse response (FIR) filters is proposed. The baseline coefficients are optimized to reduce the switching activity of the multipliers in the FIR filter, enabling the possibility of scaling the power consumption of the filter at runtime. The area as well as the leakage power of many system-on-chips is often dominated by embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to the conventional static random-access memory (SRAM) when a higher memory density is desired. However, due to GC-eDRAMs relying on many interdependent variables, the adaptation of existing memories and the design of future GCeDRAMs prove to be highly complex tasks. Thus, the first modeling tool that estimates timing, memory availability, bandwidth, and area of GC-eDRAMs for a fast exploration of their design space is proposed in this thesis

Ultra Low-power Wireless Sensor Node Design for ECG Sensing Applications

Ubiquitous computing, such as smart homes, smart cars, and smart grid, connects our world closely so that we can easily access to the world through such virtual infrastructural systems. The ultimate vision of this is Internet of Things (IoT) through which intelligent monitoring and management is feasible via networked sensors and actuators. In this system, devices transmit sensed information, and execute instructions distributed via sensor networks. A wireless sensor network (WSN) is such a network where many sensor nodes are interconnected such that a sensor node can transmit information via its adjacent sensor nodes when physical phenomenon is detected. Accordingly, the information can be delivered to the destination through this process. The concept of WSN is also applicable to biomedical applications, especially ECG sensing applications, in a form of a sensor network, so-called body sensor network (BSN), where affixed or implanted biosignal sensors gather bio-signals and transmit them to medical providers. The main challenge of BSN is energy constraint since implanted sensor nodes cannot be replaced easily, so they should prolong with a limited amount of battery energy or by energy harvesting. Thus, we will discuss several power saving techniques in this thesis.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137081/1/hesed_1.pd

Journal of Telecommunications and Information Technology, 2011, nr 4

kwartalni

Energy Efficient Servers

Computer scienc

Energy Efficient Servers

Computer scienc

NASA Tech Briefs, September 1992

Topics include: Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences; Life Sciences

Handbook of Life Course Health Development

Health development science; Developmental origins of chronic illnesses; Community; Diabetes; Autism; Obesity; Nutrition; Health disparities across the lifespan; Fetal programmin