A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems

In this paper we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware-experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results

Scalability analysis of large-scale LoRaWAN networks in ns-3

As LoRaWAN networks are actively being deployed in the field, it is important to comprehend the limitations of this Low Power Wide Area Network technology. Previous work has raised questions in terms of the scalability and capacity of LoRaWAN networks as the number of end devices grows to hundreds or thousands per gateway. Some works have modeled LoRaWAN networks as pure ALOHA networks, which fails to capture important characteristics such as the capture effect and the effects of interference. Other works provide a more comprehensive model by relying on empirical and stochastic techniques. This work uses a different approach where a LoRa error model is constructed from extensive complex baseband bit error rate simulations and used as an interference model. The error model is combined with the LoRaWAN MAC protocol in an ns-3 module that enables to study multi channel, multi spreading factor, multi gateway, bi-directional LoRaWAN networks with thousands of end devices. Using the lorawan ns-3 module, a scalability analysis of LoRaWAN shows the detrimental impact of downstream traffic on the delivery ratio of confirmed upstream traffic. The analysis shows that increasing gateway density can ameliorate but not eliminate this effect, as stringent duty cycle requirements for gateways continue to limit downstream opportunities.Comment: 12 pages, submitted to the IEEE Internet of Things Journa

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Analysis of crosstalk and field coupling to lossy MTL's in a SPICE environment

This paper proposes a circuit model for lossy multiconductor transmission lines (MTLs) suitable for implementation in modern SPICE simulators, as well as in any simulator supporting differential operators. The model includes the effects of a uniform or nonuniform disturbing field illuminating the line and is especially devised for the transient simulation of electrically long wideband interconnects with frequency dependent per-unit-length parameters. The MTL is characterized by its transient matched scattering responses, which are computed including both dc and skin losses by means of a specific algorithm for the inversion of the Laplace transform. The line characteristics are then represented in terms of differential operators and ideal delays to improve the numerical efficiency and to simplify the coding of the model in existing simulators. The model can be successfully applied to many kinds of interconnects ranging from micrometric high-resistivity metallizations to low-loss PCBs and cables, and can be considered a practical extension of the widely appreciated lossless MTL SPICE model, which maintains the simplicity and efficienc

Telemetry downlink interfaces and level-zero processing

The technical areas being investigated are as follows: (1) processing of space to ground data frames; (2) parallel architecture performance studies; and (3) parallel programming techniques. Additionally, the University administrative details and the technical liaison between New Mexico State University and Goddard Space Flight Center are addressed

Design of Cryogenic SiGe Low-Noise Amplifiers

This paper describes a method for designing cryogenic silicon-germanium (SiGe) transistor low-noise amplifiers and reports record microwave noise temperature, i.e., 2 K, measured at the module connector interface with a 50-Ω generator. A theory for the relevant noise sources in the transistor is derived from first principles to give the minimum possible noise temperature and optimum generator impedance in terms of dc measured current gain and transconductance. These measured dc quantities are then reported for an IBM SiGe BiCMOS-8HP transistor at temperatures from 295 to 15 K. The measured and modeled noise and gain for both a single- and two-transistor cascode amplifier in the 0.2-3-GHz range are then presented. The noise model is then combined with the transistor equivalent-circuit elements in a circuit simulator and the noise in the frequency range up to 20 GHz is compared with that of a typical InP HEMT