Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods

This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness and capability of built-in-self test (BIST) implementation. It can also be generalized to the oscillation based test structures of other CMOS analog and mixed-signal integrated circuits. The practical results and simulations confirm the functionality of the proposed test method

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Novel Current-Mode Sensor Interfacing and Radio Blocks for Cell Culture Monitoring

Since 2004 Imperial College has been developing the world’s first application-specific instrumentation aiming at the on-line, in-situ, physiochemical monitoring of adult stem cell cultures. That effort is internationally known as the ‘Intelligent Stem Cell Culture Systems’ (ISCCS) project. The ISCCS platform is formed by the functional integration of biosensors, interfacing electronics and bioreactors. Contrary to the PCB-level ISCCS platform the work presented in this thesis relates to the realization of a miniaturized cell culture monitoring platform. Specifically, this thesis details the synthesis and fabrication of pivotal VLSI circuit blocks suitable for the construction of a miniaturized microelectronic cell monitoring platform. The thesis is composed of two main parts. The first part details the design and operation of a two-stage current-input currentoutput topology suitable for three-electrode amperometric sensor measurements. The first stage is a CMOS-dual rail-class AB-current conveyor providing a low impedancevirtual ground node for a current input. The second stage is a novel hyperbolic-sinebased externally-linear internally-non-linear current amplification stage. This stage bases its operation upon the compressive sinh−1 conversion of the interfaced current to an intermediate auxiliary voltage and the subsequent sinh expansion of the same voltage. The proposed novel topology has been simulated for current-gain values ranging from 10 to 1000 using the parameters of the commercially available 0.8μm AMS CMOS process. Measured results from a chip fabricated in the same technology are also reported. The proposed interfacing/amplification architecture consumes 0.88-95μW. The second part describes the design and practical evaluation of a 13.56MHz frequency shift keying (FSK) short-range (5cm) telemetry link suitable for the monitoring of incubated cultures. Prior to the design of the full FSK radio system, a pair of 13.56MHz antennae are characterized experimentally. The experimental S-parameter-value determination of the 13.56MHz wireless link is incorporated into the Cadence Design Framework allowing a high fidelity simulation of the reported FSK radio. The transmitter of the proposed system is a novel multi-tapped seven-stage ring-oscillator-based VCO whereas the core of the receiver is an appropriately modified phase locked loop (PLL). Simulated and measured results from a 0.8μm CMOS technology chip are reported

High-speed communication circuits: voltage control oscillators and VCO-derived filters

Voltage Controlled Oscillators (VCO) and filters are the two main topics of focus in this dissertation.;A temperature and process compensated VCO, which is designed to operate at 2 GHz, and whose frequency variation due to incoming data is limited to 1% of its center frequency was presented. The test results show that, without process changes present, the frequency variation due to a temperature change over 0°C to 100°C is around 1.1% of its center frequency. This is a reduction of a factor of 10 when compared to the temperature variation of a conventional VCO.;A new method of designing continuous-time monolithic filters derived from well-known voltage controlled oscillators (VCOs) was introduced. These VCO-derived filters are capable of operating at very high frequencies in standard CMOS processes. Prototype low-pass and band-pass filters designed in a TSMC 0.25 mum process are discussed. Simulation results for the low-pass filter designed for a cutoff frequency of 4.3 GHz show a THD of -40 dB for a 200 mV peak-peak sinusoidal input. The band-pass filter has a resonant frequency programmable from 2.3 GHz to 3.1 GHz, a programmable Q from 3 to 85, and mid-band THD of -40 dB for an 80 mV peak-peak sinusoidal input signal.;A third contribution in this dissertation was the design of a new current mirror with accurate mirror gain for low beta bipolar transistors. High mirror gain accuracy is achieved by using a split-collector transistor to compensate for base currents of the source-coupled

Robust low power CMOS methodologies for ISFETs instrumentation

I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor (ISFET) for pH detection. In circuit design, I have developed frequency domain signal processing, which transforms pH information into a frequency modulated signal. The frequency modulated signal is subsequently digitized and encoded into a bit-stream of data. The architecture of the instrumentation system consists of a) A novel front-end averaging amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high linear voltage controlled oscillator for converting the voltage signal into a frequency modulated signal, and c) Digital gates for digitizing and differentiating the frequency modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st order sigma delta modulation, whose noise floor is shaped by +20dB/decade. The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip responds linearly to the pH in a chemical solution and produces a digital output, with up to an 8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’ threshold voltages into atypical values. As compared to other ISFET-related works in the literature, the instrumentation system proposed in this thesis can cope with the mismatched ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very accurate and robust for chemical sensing

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

8-Phase Ring oscillator for modern receivers

The evolution of receiver architectures, built in modern CMOS technologies, allows the design of high efficient receivers. A key block in modern receivers is the oscillator. The main objective of this thesis is to design a very low power and low area 8-Phase Ring Oscillator for biomedical applications (ISM and WMTS bands). Oscillators with multiphase outputs and variable duty cycles are required. In this thesis we are focused in 12.5% and 50% duty-cycles approaches. The proposed circuit uses eight inverters in a ring structure, in order to generate the output duty cycle of 50%. The duty cycle of 1/8 is achieved through the combination of the longer duty cycle signals in pairs, using, for this purpose, NAND gates. Since the general application are not only the wireless communications context, as well as industrial, scientific and medical plans, the 8-Phase Oscillator is simulated to be wideband between 100 MHz and 1 GHz, and be able to operate in the ISM bands (447 MHz-930 MHz) and WMTS (600 MHz). The circuit prototype is designed in UMC 130 nm CMOS technology. The maximum value of current drawn from a DC power source of 1.2 V, at a maximum frequency of 930 MHz achieved, is 17.54 mA. After completion of the oscillator layout studied (occupied area is 165 μm x 83 μm). Measurement results confirm the expected operating range from the simulations, and therefore, that the oscillator fulfil effectively the goals initially proposed in order to be used as Local Oscillator in RF Modern Receivers

[Delta] IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter

This work presents design, implementation and test of a built-in current sensor (BICS) for ∆IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter (DAC). The sensor uses power discharge method for the fault detection. The sensor operates in two modes, the test mode and the normal mode. In the test mode, the BICS is connected to the circuit under test (CUT) which is DAC and detects abnormal currents caused by manufacturing defects. In the normal mode, BICS is isolated from the CUT. The BICS is integrated with the DAC and is implemented in a 0.5 μm n-well CMOS technology. The DAC uses charge scaling method for the design and a low voltage (0 to 2.5 V) folded cascode op-amp. The built-in current sensor (BICS) has a resolution of 0.5 μA. Faults have been introduced into DAC using fault injection transistors (FITs). The method of ∆IDDQ testing has been verified both from simulation and experimental measurements