9 research outputs found
Calcul sur architecture non fiable
Although materials could be fabricated as error-free theoretically with a huge cost for worst-case design methodologies, the circuit is still susceptible to transient faults by the effects of radiation, temperature sensitivity, and etc. On the contrary, an error-resilient design enables the manufacturing process to be relieved from the variability issue so as to save material cost. Since variability and transient upsets are worsening as emerging fabrication process and size shrink are tending intense, the requirement of robust design is imminent. This thesis addresses the issue of designing on unreliable circuit. The main contributions are fourfold. Firstly a fast error-correction and low cost redundancy fault-tolerant method is presented. Moreover, we introduce judicious two-dimensional criteria to estimate the reliability and the hardware efïŹciency of a circuit. A general-purpose model offers low-redundancy error-resilience for contemporary logic systems as well as future nanoeletronic architectures. At last, a decoder against internal transient faults is designed in this work.En thĂ©orie, les circuits Ă©lectroniques conçus selon la mĂ©thode du pire-cas sont supposĂ©s garantir un fonctionnement sans erreur pourun coĂ»t dâimplĂ©mentation Ă©levĂ©. Dans la pratique les circuits restent sujets aux erreurs transitoires du fait de leur sensibilitĂ© aux alĂ©astels que la radiation et la tempĂ©rature. En revanche, une conception prenant en compte la tolĂ©rance aux fautes permet de faire face Ă detels alĂ©as comme la variabilitĂ© du processus de fabrication. De plus, les erreurs transitoires et la variabilitĂ© de fabrication sâintensiïŹentavec lâĂ©mergence de nouveaux processus de fabrication et des circuits de dimension de plus en plus rĂ©duite. La demande dâune conceptionintĂ©grant la tolĂ©rance aux fautes devient dĂ©sormais primordiale. La prĂ©sente thĂšse a pour objectif de cerner la problĂ©matique de laconception de circuits sur des puces peu ïŹables et apporte des contributions suivant quatre aspects. Dans un premier temps, nous proposonsune mĂ©thode de tolĂ©rance aux fautes, basĂ©e sur la correction dâerreurs et la redondance Ă faible coĂ»t. Puis, nous prĂ©sentonsun critĂšre bidimensionnel judicieux permettant dâĂ©valuer la ïŹabilitĂ© et lâefïŹcacitĂ© matĂ©rielle de circuits. Nous proposons ensuite un modĂšleuniversel qui apporte une tolĂ©rance avec fautes Ă redondance faible pour les systĂšmes logiques dâaujourdâhui et les architecturesnanoĂ©lectroniques de demain. EnïŹn, nous dĂ©couvrons un dĂ©codeur tolĂ©rant aux fautes transitoires internes
Asynchronous designs on FPGA with soft error tolerance for security algorithms
Asynchronous methodologies, such as Null Convention Logic (NCL), have tremendous potential in implementing digital logic. It is essential to design complex asynchronous circuits using commercial Electronic Design Automation (EDA) tools. The main focus of this thesis is to design NCL circuits using VHDL and implementing them on FPGAs. The major contributions of this thesis include: 1) Developing a methodology of designing NCL circuits with VHDL and applying it successfully to all practical designs in this thesis. 2) As an example, the NCL circuit for DES (Data Encryption Standard) algorithm has been designed and simulated using VHDL and the implementation issues on various FPGAs (Xilinx and Altera) have been investigated. Modification of the design has been done to minimize the amount of logic used. 3) An effective soft error tolerant scheme for asynchronous circuits on FPGAs is proposed, and successfully verified through software simulation and hardware implementation by introducing it into a DES round. This thesis provides a starting point for further investigation of NCL circuits, in terms of VHDL modeling, FPGA implementations, and soft error tolerance
Methodologies and Toolflows for the Predictable Design of Reliable and Low-Power NoCs
There is today the unmistakable need to evolve design methodologies and
tool
ows for Network-on-Chip based embedded systems. In particular, the
quest for low-power requirements is nowadays a more-than-ever urgent dilemma.
Modern circuits feature billion of transistors, and neither power management
techniques nor batteries capacity are able to endure the increasingly higher
integration capability of digital devices. Besides, power concerns come together
with modern nanoscale silicon technology design issues.
On one hand, system failure rates are expected to increase exponentially at
every technology node when integrated circuit wear-out failure mechanisms
are not compensated for. However, error detection and/or correction mechanisms
have a non-negligible impact on the network power.
On the other hand, to meet the stringent time-to-market deadlines, the design
cycle of such a distributed and heterogeneous architecture must not be
prolonged by unnecessary design iterations.
Overall, there is a clear need to better discriminate reliability strategies and
interconnect topology solutions upfront, by ranking designs based on power
metric. In this thesis, we tackle this challenge by proposing power-aware
design technologies.
Finally, we take into account the most aggressive and disruptive methodology
for embedded systems with ultra-low power constraints, by migrating
NoC basic building blocks to asynchronous (or clockless) design style. We
deal with this challenge delivering a standard cell design methodology and
mainstream CAD tool
ows, in this way partially relaxing the requirement
of using asynchronous blocks only as hard macros
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On Multicast in Asynchronous Networks-on-Chip: Techniques, Architectures, and FPGA Implementation
In this era of exascale computing, conventional synchronous design techniques are facing unprecedented challenges. The consumer electronics market is replete with many-core systems in the range of 16 cores to thousands of cores on chip, integrating multi-billion transistors. However, with this ever increasing complexity, the traditional design approaches are facing key issues such as increasing chip power, process variability, aging, thermal problems, and scalability. An alternative paradigm that has gained significant interest in the last decade is asynchronous design. Asynchronous designs have several potential advantages: they are naturally energy proportional, burning power only when active, do not require complex clock distribution, are robust to different forms of variability, and provide ease of composability for heterogeneous platforms. Networks-on-chip (NoCs) is an interconnect paradigm that has been introduced to deal with the ever-increasing system complexity. NoCs provide a distributed, scalable, and efficient interconnect solution for todayâs many-core systems. Moreover, NoCs are a natural match with asynchronous design techniques, as they separate communication infrastructure and timing from the computational elements. To this end, globally-asynchronous locally-synchronous (GALS) systems that interconnect multiple processing cores, operating at different clock speeds, using an asynchronous NoC, have gained significant interest. While asynchronous NoCs have several advantages, they also face a key challenge of supporting new types of traffic patterns. Once such pattern is multicast communication, where a source sends packets to arbitrary number of destinations. Multicast is not only common in parallel computing, such as for cache coherency, but also for emerging areas such as neuromorphic computing. This important capability has been largely missing from asynchronous NoCs. This thesis introduces several efficient multicast solutions for these interconnects. In particular, techniques, and network architectures are introduced to support high-performance and low-power multicast. Two leading network topologies are the focus: a variant mesh-of-trees (MoT) and a 2D mesh. In addition, for a more realistic implementation and analysis, as well as significantly advancing the field of asynchronous NoCs, this thesis also targets synthesis of these NoCs on commercial FPGAs. While there has been significant advances in FPGA technologies, there has been only limited research on implementing asynchronous NoCs on FPGAs. To this end, a systematic computeraided design (CAD) methodology has been introduced to efficiently and safely map asynchronous NoCs on FPGAs. Overall, this thesis makes the following three contributions. The first contribution is a multicast solution for a variant MoT network topology. This topology consists of simple low-radix switches, and has been used in high-performance computing platforms. A novel local speculation technique is introduced, where a subset of the networkâs switches are speculative that always broadcast every packet. These switches are very simple and have high performance. Speculative switches are surrounded by non-speculative ones that route packets based on their destinations and also throttle any redundant copies created by the former. This hybrid network architecture achieved significant performance and power benefits over other multicast approaches. The second contribution is a multicast solution for a 2D-mesh topology, which is more complex with higher-radix switches and also is more commonly used. A novel continuous-time replication strategy is introduced to optimize the critical multi-way forking operation of a multicast transmission. In this technique, a multicast packet is first stored in an input port of a switch, from where it is sent through distinct output ports towards different destinations concurrently, at each outputâs own rate and in continuous time. This strategy is shown to have significant latency and energy benefits over an approach that performs multicast using multiple distinct serial unicasts to each destination. Finally, a systematic CAD methodology is introduced to synthesize asynchronous NoCs on commercial FPGAs. A two-fold goal is targeted: correctness and high performance. For ease of implementation, only existing FPGA synthesis tools are used. Moreover, since asynchronous NoCs involve special asynchronous components, a comprehensive guide is introduced to map these elements correctly and efficiently. Two asynchronous NoC switches are synthesized using the proposed approach on a leading Xilinx FPGA in 28 nm: one that only handles unicast, and the other that also supports multicast. Both showed significant energy benefits with some performance gains over a state-of-the-art synchronous switch
Test and Testability of Asynchronous Circuits
The ever-increasing transistor shrinkage and higher clock frequencies are causing serious clock distribution, power management, and reliability issues. Asynchronous design is predicted to have a significant role in tackling these challenges because of its distributed control mechanism and on-demand, rather than continuous, switching activity.
Null Convention Logic (NCL) is a robust and low-power asynchronous paradigm that introduces new challenges to test and testability algorithms because 1) the lack of deterministic timing in NCL complicates the management of test timing, 2) all NCL gates are state-holding and even simple combinational circuits show sequential behaviour, and 3) stuck-at faults on gate internal feedback (GIF) of NCL gates do not always cause an incorrect output and therefore are undetectable by automatic test pattern generation (ATPG) algorithms.
Existing test methods for NCL use clocked hardware to control the timing of test. Such test hardware could introduce metastability issues into otherwise highly robust NCL devices. Also, existing test techniques for NCL handle the high-statefulness of NCL circuits by excessive incorporation of test hardware which imposes additional area, propagation delay and power consumption.
This work, first, proposes a clockless self-timed ATPG that detects all faults on the gate inputs and a share of the GIF faults with no added design for test (DFT). Then, the efficacy of quiescent current (IDDQ) test for detecting GIF faults undetectable by a DFT-less ATPG is investigated. Finally, asynchronous test hardware, including test points, a scan cell, and an interleaved scan architecture, is proposed for NCL-based circuits. To the extent of our knowledge, this is the first work that develops clockless, self-timed test techniques for NCL while minimising the need for DFT, and also the first work conducted on IDDQ test of NCL.
The proposed methods are applied to multiple NCL circuits with up to 2,633 NCL gates (10,000 CMOS Boolean gates), in 180 and 45 nm technologies and show average fault coverage of 88.98% for ATPG alone, 98.52% including IDDQ test, and 99.28% when incorporating test hardware. Given that this fault coverage includes detection of GIF faults, our work has 13% higher fault coverage than previous work. Also, because our proposed clockless test hardware eliminates the need for double-latching, it reduces the average area and delay overhead of previous studies by 32% and 50%, respectively
Architectural Exploration of KeyRing Self-Timed Processors
RĂSUMĂ
Les derniĂšres dĂ©cennies ont vu lâaugmentation des performances des processeurs contraintes
par les limites imposĂ©es par la consommation dâĂ©nergie des systĂšmes Ă©lectroniques : des trĂšs
basses consommations requises pour les objets connectés, aux budgets de dépenses électriques
des serveurs, en passant par les limitations thermiques et la durée de vie des batteries des
appareils mobiles. Cette forte demande en processeurs efficients en énergie, couplée avec
les limitations de la rĂ©duction dâĂ©chelle des transistorsâqui ne permet plus dâamĂ©liorer les
performances Ă densitĂ© de puissance constanteâ, conduit les concepteurs de circuits intĂ©grĂ©s
Ă explorer de nouvelles microarchitectures permettant dâobtenir de meilleures performances
pour un budget Ă©nergĂ©tique donnĂ©. Cette thĂšse sâinscrit dans cette tendance en proposant
une nouvelle microarchitecture de processeur, appelĂ©e KeyRing, conçue avec lâintention de
rĂ©duire la consommation dâĂ©nergie des processeurs.
La frĂ©quence dâopĂ©ration des transistors dans les circuits intĂ©grĂ©s est proportionnelle Ă leur
consommation dynamique dâĂ©nergie. Par consĂ©quent, les techniques de conception permettant
de réduire dynamiquement le nombre de transistors en opération sont trÚs largement
adoptĂ©es pour amĂ©liorer lâefficience Ă©nergĂ©tique des processeurs. La technique de clock-gating
est particuliĂšrement usitĂ©e dans les circuits synchrones, car elle rĂ©duit lâimpact de lâhorloge
globale, qui est la principale source dâactivitĂ©. La microarchitecture KeyRing prĂ©sentĂ©e dans
cette thÚse utilise une méthode de synchronisation décentralisée et asynchrone pour réduire
lâactivitĂ© des circuits. Elle est dĂ©rivĂ©e du processeur AnARM, un processeur dĂ©veloppĂ© par
Octasic sur la base dâune microarchitecture asynchrone ad hoc. Bien quâil soit plus efficient
en Ă©nergie que des alternatives synchrones, le AnARM est essentiellement incompatible avec
les mĂ©thodes de synthĂšse et dâanalyse temporelle statique standards. De plus, sa technique
de conception ad hoc ne sâinscrit que partiellement dans les paradigmes de conceptions asynchrones.
Cette thÚse propose une approche rigoureuse pour définir les principes généraux
de cette technique de conception ad hoc, en faisant levier sur la littérature asynchrone. La
microarchitecture KeyRing qui en résulte est développée en association avec une méthode
de conception automatisĂ©e, qui permet de sâaffranchir des incompatibilitĂ©s natives existant
entre les outils de conception et les systÚmes asynchrones. La méthode proposée permet de
pleinement mettre Ă profit les flots de conception standards de lâindustrie microĂ©lectronique
pour réaliser la synthÚse et la vérification des circuits KeyRing. Cette thÚse propose également
des protocoles expérimentaux, dont le but est de renforcer la relation de causalité
entre la microarchitecture KeyRing et une réduction de la consommation énergétique des
processeurs, comparativement Ă des alternatives synchrones Ă©quivalentes.----------ABSTRACT
Over the last years, microprocessors have had to increase their performances while keeping
their power envelope within tight bounds, as dictated by the needs of various markets: from
the ultra-low power requirements of the IoT, to the electrical power consumption budget
in enterprise servers, by way of passive cooling and day-long battery life in mobile devices.
This high demand for power-efficient processors, coupled with the limitations of technology
scalingâwhich no longer provides improved performances at constant power densitiesâ, is
leading designers to explore new microarchitectures with the goal of pulling more performances
out of a fixed power budget. This work enters into this trend by proposing a new
processor microarchitecture, called KeyRing, having a low-power design intent.
The switching activity of integrated circuitsâi.e. transistors switching on and offâdirectly
affects their dynamic power consumption. Circuit-level design techniques such as clock-gating
are widely adopted as they dramatically reduce the impact of the global clock in synchronous
circuits, which constitutes the main source of switching activity. The KeyRing microarchitecture
presented in this work uses an asynchronous clocking scheme that relies on decentralized
synchronization mechanisms to reduce the switching activity of circuits. It is derived from
the AnARM, a power-efficient ARM processor developed by Octasic using an ad hoc asynchronous
microarchitecture. Although it delivers better power-efficiency than synchronous
alternatives, it is for the most part incompatible with standard timing-driven synthesis and
Static Timing Analysis (STA). In addition, its design style does not fit well within the existing
asynchronous design paradigms. This work lays the foundations for a more rigorous
definition of this rather unorthodox design style, using circuits and methods coming from the
asynchronous literature. The resulting KeyRing microarchitecture is developed in combination
with Electronic Design Automation (EDA) methods that alleviate incompatibility issues
related to ad hoc clocking, enabling timing-driven optimizations and verifications of KeyRing
circuits using industry-standard design flows. In addition to bridging the gap with standard
design practices, this work also proposes comprehensive experimental protocols that aims to
strengthen the causal relation between the reported asynchronous microarchitecture and a
reduced power consumption compared with synchronous alternatives.
The main achievement of this work is a framework that enables the architectural exploration
of circuits using the KeyRing microarchitecture
Space Station Furnace Facility. Volume 2: Summary of technical reports
The Space Station Furnace Facility (SSFF) is a modular facility for materials research in the microgravity environment of the Space Station Freedom (SSF). The SSFF is designed for crystal growth and solidification research in the fields of electronic and photonic materials, metals and alloys, and glasses and ceramics, and will allow for experimental determination of the role of gravitational forces in the solidification process. The facility will provide a capability for basic scientific research and will evaluate the commercial viability of low-gravity processing of selected technologically important materials. In order to accommodate the furnace modules with the resources required to operate, SSFF developed a design that meets the needs of the wide range of furnaces that are planned for the SSFF. The system design is divided into subsystems which provide the functions of interfacing to the SSF services, conditioning and control for furnace module use, providing the controlled services to the furnace modules, and interfacing to and acquiring data from the furnace modules. The subsystems, described in detail, are as follows: Power Conditioning and Distribution Subsystem; Data Management Subsystem; Software; Gas Distribution Subsystem; Thermal Control Subsystem; and Mechanical Structures Subsystem