Estimating the cost of generic quantum pre-image attacks on SHA-2 and SHA-3

We investigate the cost of Grover's quantum search algorithm when used in the context of pre-image attacks on the SHA-2 and SHA-3 families of hash functions. Our cost model assumes that the attack is run on a surface code based fault-tolerant quantum computer. Our estimates rely on a time-area metric that costs the number of logical qubits times the depth of the circuit in units of surface code cycles. As a surface code cycle involves a significant classical processing stage, our cost estimates allow for crude, but direct, comparisons of classical and quantum algorithms. We exhibit a circuit for a pre-image attack on SHA-256 that is approximately $2^{153.8}$ surface code cycles deep and requires approximately $2^{12.6}$ logical qubits. This yields an overall cost of $2^{166.4}$ logical-qubit-cycles. Likewise we exhibit a SHA3-256 circuit that is approximately $2^{146.5}$ surface code cycles deep and requires approximately $2^{20}$ logical qubits for a total cost of, again, $2^{166.5}$ logical-qubit-cycles. Both attacks require on the order of $2^{128}$ queries in a quantum black-box model, hence our results suggest that executing these attacks may be as much as $275$ billion times more expensive than one would expect from the simple query analysis.Comment: Same as the published version to appear in the Selected Areas of Cryptography (SAC) 2016. Comments are welcome

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions

Secure Cryptographic Algorithm for a Fault Tolerant model in Unmanned Aerial Vehicles

AES (Advanced Encryption Standard), provides the highest level of security by utilizing the strongest 128 bit Al-gorithm to encrypt and authenticate the data. AES commercial security algorithm has proved to be effective in Unmanned Aerial vehicles which is used for military purpose such as enemy tracking , environmental monitoring meteorology, map making etc .The demand to protect the sensitive and valuable data transmitted from UAV ( Unmanned Aerial Vehicles ) to ground has increased in Defense and hence the need to use onboard encryption . In order to avoid data corruption due to single even upsets (SEU’s) a novel fault tolerant model of AES is presented which is based on the Hamming error cor-rection code. For this work a problem was chosen that first addresses the encryption of UAV imaging data using the effi-cient AES CBC mode .A detailed analysis of the effect of single even upsets (SEUs) on imaging data during on-board encryption is carried out. The impact of faults in the data oc-curring during transmission to ground due to noisy channels is analyzed .The performance for the above fault tolerant model is measured using power and throughput

Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication

We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example. 1

Entwurfsmethodologie für höchst zuverlässige digitale ASIC-Designs angewandt auf Network-Centric System Middleware Switch Prozessor

The sensitivity of application-specific integrated circuits (ASICs) to single event effects (SEE) can lead to failures of subsystems which are exposed to increased radiation levels in space and on the ground. The work described in this thesis presents a design methodology for a fully fault-tolerant ASIC that is immune to single event upset effects (SEU) in sequential logic, single event transient effects (SET) in combinatorial logic, and single event latchup effects (SEL). Redundant circuits combined with SEL power switches (SPS) are the basis for a design methodology which achieves this goal. Within the standard ASIC design flow enhancements were made in order to incorporate redundancy and SPS cells and, consequently, enable protection against SEU, SET, and SEL. In order to validate the resulting fault-tolerant circuits a fault-injection environment with carefully designed fault models was developed. The moments of fault occurrence and their durations are modeled according to the real effects in actual hardware. The proposed design methodology was applied to an innovative space craft area network (SCAN) central processor unit, known as middleware switch processor. The measurement results presented in this thesis prove the correct functionality of DMR and SPS circuits, as well as the high fault-tolerance of the implemented ASICs along with moderate overhead with respect to power consumption and occupied silicon area. Irradiation measurements demonstrated the correct design and successful implementation of the SPS cell.Die Empfindlichkeit von anwendungsspezifischen integrierten Schaltungen (ASICs) zu den einzelnen Ereigniseffekten (SEE), kann zu Ausfällen von Subsystemen führen, die erhöhten Strahlungspegeln im Raum und auf dem Boden ausgesetzt werden. Die Arbeit, die in dieser Thesis beschrieben wird, stellt eine Entwurfsmethodologie vor um fehlertolerante ASICs zu entwerfen, welche die immun gegen singuläre Störung Effekte (SEU) in sequentielle Logik ist, einzelne Ereignis vorübergehende Effekte (SET) in der kombinatorischen Logik und einzelnes Ereignis Latchup-Effekte (SEL). Modulare Redundanz und SEL-Schalter (SPS) sind die Basis für eine Design-Methodik, die volle fehlertolerante ASIC liefert. Der Standard ASIC-Designflow ist erweitert worden, um Redundanz mit SPS-Schalter zu enthalten und Schutz gegen SEU, SET und SEL zu ermöglichen. Um die fehlertoleranten Stromkreise zu validieren ist eine Fault-Injektion Umgebung mit Fault Modellen entwickelt worden. Die Momente des Auftretens und der Dauer der injizierten Fehler werden entsprechend den realen Effekten in die Hardware modelliert. Die Methodologie des vorgeschlagenen Entwurfs ist an einem innovativen Space Craft Area Network (SCAN) Schaltkreis angewendet worden, bekannt als Middleware Switch Prozessor. Die Messergebnisse, die in dieser These dargestellt werden, haben die korrekte Funktionalität von Redundanz- und SPS-Stromkreisen sowie die hohe Fehler-Toleranz der resultierende ASICs zusammen mit mäßigen Unkosten in Bezug auf Leistungsaufnahme und besetzten Silikonfläche nachgewiesen. Die Strahlungsmessungen haben das korrekte Design und die erfolgreiche Umsetzung der SPS-Zelle bewiesen

Interconnect yield analysis and fault tolerance for field programmable gate arrays

Imperial Users onl

FPGAs in Industrial Control Applications

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability