Multilayer optical learning networks

A new approach to learning in a multilayer optical neural network based on holographically interconnected nonlinear devices is presented. The proposed network can learn the interconnections that form a distributed representation of a desired pattern transformation operation. The interconnections are formed in an adaptive and self-aligning fashioias volume holographic gratings in photorefractive crystals. Parallel arrays of globally space-integrated inner products diffracted by the interconnecting hologram illuminate arrays of nonlinear Fabry-Perot etalons for fast thresholding of the transformed patterns. A phase conjugated reference wave interferes with a backward propagating error signal to form holographic interference patterns which are time integrated in the volume of a photorefractive crystal to modify slowly and learn the appropriate self-aligning interconnections. This multilayer system performs an approximate implementation of the backpropagation learning procedure in a massively parallel high-speed nonlinear optical network

Optically interconnected phased arrays

Phased-array antennas are required for many future NASA missions. They will provide agile electronic beam forming for communications and tracking in the range of 1 to 100 GHz. Such phased arrays are expected to use several hundred GaAs monolithic integrated circuits (MMICs) as transmitting and receiving elements. However, the interconnections of these elements by conventional coaxial cables and waveguides add weight, reduce flexibility, and increase electrical interference. Alternative interconnections based on optical fibers, optical processing, and holography are under evaluation as possible solutions. In this paper, the current status of these techniques is described. Since high-frequency optical components such as photodetectors, lasers, and modulators are key elements in these interconnections, their performance and limitations are discussed

A candidate architecture for monitoring and control in chemical transfer propulsion systems

To support the exploration of space, a reusable space-based rocket engine must be developed. This engine must sustain superior operability and man-rated levels of reliability over several missions with limited maintenance or inspection between flights. To meet these requirements, an expander cycle engine incorporating a highly capable control and health monitoring system is planned. Alternatives for the functional organization and the implementation architecture of the engine's monitoring and control system are discussed. On the basis of this discussion, a decentralized architecture is favored. The trade-offs between several implementation options are outlined and future work is proposed

Advanced digital SAR processing study

A highly programmable, land based, real time synthetic aperture radar (SAR) processor requiring a processed pixel rate of 2.75 MHz or more in a four look system was designed. Variations in range and azimuth compression, number of looks, range swath, range migration and SR mode were specified. Alternative range and azimuth processing algorithms were examined in conjunction with projected integrated circuit, digital architecture, and software technologies. The advaced digital SAR processor (ADSP) employs an FFT convolver algorithm for both range and azimuth processing in a parallel architecture configuration. Algorithm performace comparisons, design system design, implementation tradeoffs and the results of a supporting survey of integrated circuit and digital architecture technologies are reported. Cost tradeoffs and projections with alternate implementation plans are presented

Optoelectronic parallel-matching architecture : architecture description, performance estimation, and prototype demonstration

This paper was published in Optics Express and is made available as an electronic reprint with the permission of OSA. The paper can be found at the following URL on the OSA website: http://dx.doi.org/10.1364/AO.40.000283 Systematic or multiple reproduction or distribution to multiple locations via electronic or other means is prohibited and is subject to penalties under law

3D multi-layer vision architecture for surveillance and reconnaissance applications

The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is integrated via bump bonding technology. The chip is constructed of a 320 x 240 sensor array layer, closely coupled with a 160 x 120 mixed-signal processor array layer, a digital frame buffer layer, and an 8 x 8 digital fovea processor array layer. The chip is designed to solve image registration and feature extraction above 1000FPS.Office of Naval Research (USA) N00173-08-C-400

Energy-efficiency improvements for optical access

This article discusses novel approaches to improve energy efficiency of different optical access technologies, including time division multiplexing passive optical network (TDM-PON), time and wavelength division multiplexing PON (TWDM-PON), point-to-point (PTP) access network, wavelength division multiplexing PON (WDM-PON), and orthogonal frequency division multiple access PON (OFDMA-PON). These approaches include cyclic sleep mode, energy-efficient bit interleaving protocol, power reduction at component level, or frequency band selection. Depending on the target optical access technology, one or a combination of different approaches can be applied

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC