A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

A 300-800MHz Tunable Filter and Linearized LNA applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver

A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.\ud \u

RF transceiver design for electronic toll collection system (ETC) using compact dipole antenna

Electronic Toll Collection (ETC) system is one of the types of traffic control system that has rapid development in the recent years. ETC system is one of the major applications of Dedicated Short Range Communication (DSRC) which operates in the frequency band of 5.8GHz, used for the transfer of information between the road side unit (RSU) and the on board unit (OBU) which are situated at the toll station and on the vehicle respectively. The working of the system is based on RFID technology. ETC system is implemented in the 0.18microm CMOS technology, which is an aggressive technology in terms of its low cost and easy integration of the RF circuits.;A compact dipole antenna based low-cost RF transceiver for ETC system is designed in this thesis. Amplitude Shift Keying (ASK) modulation technique is employed in the implemented RF transceiver. In transmitter side, a class-E power amplifier is used to amplify the signal power. In order to send and receive the signal, a dipole antenna operating at a frequency of 5.8GHz is used. A low-power and energy efficient Low-Noise Amplifier (LNA) is used in the receiver block which consumes very less power and has a minimal noise figure compared with prior arts. A self-mixer is used for the down-conversion of the signal. Results of this design demonstrate the working of the transceiver at 5.8GHz frequency up to an input data rate of 400 Mbps

Power supply current [IPS] based testing of CMOS amplifier circuit with and without floating gate input transistors

This work presents a case study, which attempts to improve the fault diagnosis and testability of the power supply current based testing methodology applied to a typical two-stage CMOS operational amplifier and is extended to operational amplifier with floating gate input transistors*. The proposed test method takes the advantage of good fault coverage through the use of a simple power supply current measurement based test technique, which only needs an ac input stimulus at the input and no additional circuitry. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. In the present work, variations of ac ripple in the power supply current IPS, passing through VDD under the application of an ac input stimulus is measured to detect injected faults in the CMOS amplifier. The effect of parametric variation is taken into consideration by setting tolerance limit of ± 5% on the fault-free IPS value. The fault is identified if the power supply current, IPS falls outside the deviation given by the tolerance limit. This method presented can also be generalized to the test structures of other floating-gate MOS analog and mixed signal integrated circuits

Analog Signal Processing Elements for Energy-Constrained Platforms

Energy constrained processing poses a number of challenges that have resulted in tremendous innovations over the past decade. Shrinking supply voltages and limited clock speeds have placed an emphasis on processing efficiency over the raw throughput of a processor. One of the approaches to increase processing efficiency is to use parallel processing with slower, lower resolution processing elements. By utilizing this parallel approach, power consumption can be decreased while maintaining data throughput relative to other more power-hungry architectures.;This low resolution / parallel architecture has direct application in the analog as well as the digital domain. Indeed, research shows that as the resolution of a signal processor falls below a system-dependent threshold, it is almost always more efficient to preform the processing in the analog domain. These continuous-time circuits have long been used in the most energy-constrained applications, ranging from pacemakers and cochlear implants to wireless sensor motes designed to run autonomously for months in the field.;Most audio processing techniques utilize spectral decomposition as the first step of their algorithms, whether by a FFT/DFT in the digital domain or a bank of bandpass filters in the analog domain. The work presented here is designed to function within the parallel, array-based environment of a bank of bandpass filters. Work to improve the simulation of programmable analog storage elements (Floating-Gate transistors) in typical SPICE-based simulators is presented, along with a novel method of harnessing the unique properties of these Floating-Gate (FG) transistors to extend the linear range of a differential pair. These improvements in simulation and linearity are demonstrated in a Variable-Gain Amplfier (VGA) to compress large differential inputs into small single-ended outputs suitable for processing by other analog elements. Finally, a novel circuit composed of only six transistors is proposed to compute the continuous-time derivative of a signal within the sub-banded architecture of the bandpass filter bank

Cmos Rotary Traveling Wave Oscillators (Rtwos)

Rotary Traveling Wave Oscillator (RTWO) represents a transmission line based technology for multi-gigahertz multiple phase clock generation. RTWO is known for providing low jitter and low phase noise signals but the issue of high power consumption is a major drawback in its application. Direction of wave propagation is random and is determined by the least resistance path in the absence of an external direction control circuit. The objective of this research is to address some of the problems of RTWO design, including high power consumption, uncertainty of propagation direction and optimization of design variables. Included is the modeling of RTWO for sensitivity, phase noise and power analysis. Research objectives were met through design, simulation and implementation. Different designs of RTWO in terms of ring size and number of amplifier stages were implemented and tested. Design tools employed include Agilent ADS, Cadence EDA, SONNET and Altium PCB Designer. Test chip was fabricated using IBM 0.18 μm RF CMOS technology. Performance measures of interest are tuning range, phase noise and power consumption. Agilent ADS and SONNET were used for electromagnetic modeling of transmission lines and electromagnetic field radiation. For each design, electromagnetic simulations were carried out followed by oscillation synthesis based on circuit simulation in Cadence Spectre. RTWO frequencies between 2 GHz and 12 GHz were measured based on the ring size of transmission lines. Simulated microstrip transmission line segments had a quality factor between 5.5 and 18. For the various designs, power consumption ranged from 20 mW to 120 mW. Measured phase noise ranged between -123 dBc/Hz and -87 dBc/Hz at 1 MHz offset. Development also included the design of a wide band buffer and a printed circuit board with high signal integrity for accurate measurement of oscillation frequency and other performance measures. Simulated performance, schematics and measurement results are presented

Design of an ultra-low-power integrated amplifier for cardiac signal implantable sensors

Al giorno d'oggi, il monitoraggio della salute è un'area di ricerca cruciale, data la crescente necessità di rilevare i parametri vitali per ottenere diagnosi accurate in tempi brevi, raccogliere continuamente informazioni sullo stato di salute dei pazienti e intervenire rapidamente in circostanze critiche. Questa tesi si colloca nell'ambito della registrazione di segnali ECG, essendo di estrema importanza per la diagnosi delle malattie cardiovascolari. I dispositivi impiantabili sono spesso utilizzati per questo scopo, in quanto consentono misurazioni poco invasive, ottenendo così segnali affidabili con una migliore reiezione di interferenze e artefatti. Viene presentato un amplificatore a bassissima potenza per sensori impiantabili. Il sistema nel suo complesso ha una batteria di capacità limitata, il che rende il consumo di potenza un aspetto fondamentale nelle scelte di progettazione. Inoltre, i segnali ECG hanno un'ampiezza limitata e sono spesso affetti da ampi offset in DC, evidenziando così la necessità di progettare amplificatori accoppiati in AC, che introducano livelli di rumore minimi. Questa topologia circuitale impiega amplificatori operazionali di transconduttanza (OTA) realizzati con inverter di tipo stacked, che sommano ciascuna transconduttanza, utilizzando la stessa corrente, implementando quindi la tecnica del riutilizzo di corrente, al fine di migliorare l'efficienza di rumore e di potenza, fornendo al contempo un elevato guadagno. Il progetto è stato implementato in un processo CMOS a 130 nm. Si presenta quindi un amplificatore operazionale di transconduttanza basato su inverter di tipo stacked, pensato per processare segnali ECG. Esso presenta un guadagno di modo differenziale pari a 23.9 dB in banda, una larghezza di banda di 10.5 kHz, un rapporto di reiezione di modo comune CMRR di 59 dB, un rapporto di reiezione della tensione di alimentazione PSRR di 62 dB e rumore termico pari a 116 nV/Hz.Nowadays, health monitoring is a crucial area of research, given the increasing need to detect vital parameters in order to obtain accurate diagnoses in a short time, continuously collect informations about the health status of patients, and quickly intervene in critical circumstances. This thesis focuses on electrocardiogram (ECG) signals recording, being of the utmost importance for the diagnosis of cardiovascular diseases. Implantable devices are often used for this purpose, because they allow unobtrusive measurements, resulting in reliable signals with better rejection of interferences and artifacts. An ultra-low power amplifier intended for implantable sensors is presented. The overall system has a limited battery capacity, thus making power consumption a key aspect when it comes to design choices. Furthermore, ECG signals have a limited amplitude and are often affected by large DC offsets, thus emphasizing the need to design ac-coupled amplifiers that introduce minimal noise levels. This circuit topology employs stacked inverter-based operational transconductance amplifiers (OTAs), that add up each transconductance, but using the same current, thereby implementing the current-reuse technique, in order to improve noise and power efficiency, while providing high gain. The design was implemented in a 130-nm CMOS process. A stacked inverter-based operational transconductance amplifier (OTA) designed to process ECG signals is then presented. It achieves a differential mode gain of 23.9 dB in-band, a bandwidth of 10.5 kHZ, a common-mode rejection ratio CMRR of 59 dB, a power supply rejection ratio PSRR of 62 dB and thermal noise of 116 nV/Hz