Traffic congestion in interconnected complex networks

Traffic congestion in isolated complex networks has been investigated extensively over the last decade. Coupled network models have recently been developed to facilitate further understanding of real complex systems. Analysis of traffic congestion in coupled complex networks, however, is still relatively unexplored. In this paper, we try to explore the effect of interconnections on traffic congestion in interconnected BA scale-free networks. We find that assortative coupling can alleviate traffic congestion more readily than disassortative and random coupling when the node processing capacity is allocated based on node usage probability. Furthermore, the optimal coupling probability can be found for assortative coupling. However, three types of coupling preferences achieve similar traffic performance if all nodes share the same processing capacity. We analyze interconnected Internet AS-level graphs of South Korea and Japan and obtain similar results. Some practical suggestions are presented to optimize such real-world interconnected networks accordingly.Comment: 8 page

Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs

Future nano-scale electronics built up from an Avogadro number of components needs efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches. In recent years, the Networks-on-Chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics. Current NoC architectures are either highly regular or fully customized, both of which represent implausible assumptions for emerging bottom-up self-assembled molecular electronics that are generally assumed to have a high degree of irregularity and imperfection. Here, we pragmatically and experimentally investigate important design trade-offs and properties of an irregular, abstract, yet physically plausible 3D small-world interconnect fabric that is inspired by modern network-on-chip paradigms. We vary the framework's key parameters, such as the connectivity, the number of switch nodes, the distribution of long- versus short-range connections, and measure the network's relevant communication characteristics. We further explore the robustness against link failures and the ability and efficiency to solve a simple toy problem, the synchronization task. The results confirm that (1) computation in irregular assemblies is a promising and disruptive computing paradigm for self-assembled nano-scale electronics and (2) that 3D small-world interconnect fabrics with a power-law decaying distribution of shortcut lengths are physically plausible and have major advantages over local 2D and 3D regular topologies