60 research outputs found

    Deteksi Citra Kendaraan Berbasis Web Menggunakan Javascript Framework Library

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    Populasi penduduk yang semakin berkembang menyebabkan tingginya kemacetan jalan. Kemacetan terjadi karena jumlah kendaraan yang beroperasi tidak sebanding dengan volume jalan yang tersedia. Pemerintah sebagai pelaksana pelayanan bagi masyarakat belum mampu memberikan informasi lalu lintas yang memadai. Masyarakat membutuhkan informasi kondisi lalu lintas secara realtime, otomatis dan mudah diakses menggunakan internet. Penelitian ini bertujuan untuk memberikan informasi jumlah kendaraan dengan konsep internet of things menggunakan javascript detection library. Penelitian ini terdiri dari beberapa tahapan penelitian antara lain: survei & identifikasi, analisis data, training data, dan pengembangan aplikasi menggunakan javascript framework library. Hasil yang didapatkan adalah aplikasi mampu mendeteksi citra kendaraan berdasarkan xml training dari Matlab sebesar 95%

    Dynamic Resource Provisioning and Scheduling in SDN/NFV-Enabled Core Networks

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    The service-oriented fifth-generation (5G) core networks are featured by customized network services with differentiated quality-of-service (QoS) requirements, which can be provisioned through network slicing enabled by the software defined networking (SDN) and network function virtualization (NFV) paradigms. Multiple network services are embedded in a common physical infrastructure, generating service-customized network slices. Each network slice supports a composite service via virtual network function (VNF) chaining, with dedicated packet processing functionality at each VNF. For a network slice with a target traffic load, the end-to-end (E2E) service delivery is enabled by VNF placement at NFV nodes (e.g., data centers and commodity servers) and traffic routing among corresponding NFV nodes, with static resource allocations. To provide continuous QoS performance guarantee over time, it is essential to develop dynamic resource management schemes for the embedded services experiencing traffic dynamics in different time granularities during virtual network operation. In this thesis, we focus on processing resources and investigate three research problems on dynamic processing resource provisioning and scheduling for embedded delay-sensitive services, in presence of both large-timescale traffic statistical changes and bursty traffic dynamics in smaller time granularities. In problem I, we investigate a dynamic flow migration problem for multiple embedded services, to accommodate the large-timescale changes in the average traffic rates with average E2E delay guarantee, while addressing a trade-off between load balancing and flow migration overhead. We develop optimization problem formulations and efficient heuristic algorithms, based on a simplified M/M/1 queueing model with Poisson traffic arrivals. Motivated by the limitations of Poisson traffic model, in problem II, we restrict to a local network scenario and study a dynamic VNF scaling problem based on a real-world traffic trace with nonstationary traffic statistics in large timescale. Under the assumption that the nonstationary traffic trace can be partitioned into non-overlapping stationary traffic segments with unknown change points in time, a change point detection driven traffic parameter learning and resource demand prediction scheme is proposed, based on which dynamic VNF migration decisions are made at variable-length decision epochs via deep reinforcement learning. The long-term trade-off between load balancing and migration overhead is studied. A fractional Brownian motion (fBm) traffic model is employed for each detected stationary traffic segment, based on properties of Gaussianity and self-similarity of the real-world traffic. In Problem III, we focus on a sufficiently long time duration with given VNF placement and stationary traffic statistics, and study a delay-aware VNF scheduling problem to coordinate VNF scheduling for multiple services, which achieves network utility maximization with timely throughput guarantee for each service, in presence of bursty and unpredictable small-timescale traffic dynamics, while using a realistic state-of-the-art time quantum (slot) for CPU processing resource scheduling among VNF software processes. Based on the Lyapunov optimization technique, an online distributed VNF scheduling algorithm is derived, which greedily schedules a VNF at each NFV node based on a weight incorporating the backpressure-based weighted differential backlogs with the downstream VNF, the service throughput performance indicated by virtual queue lengths, and the packet delay. With the proposed dynamic resource management framework, resources can be efficiently and fairly allocated to the embedded services, to avoid congestion and QoS degradation in the presence of traffic dynamics. This research provides some insights in dynamic resource management for delay-sensitive services in a virtualized network environment with CPU processing resources

    Vorhersagbares und zur Laufzeit adaptierbares On-Chip Netzwerk für gemischt kritische Echtzeitsysteme

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    The industry of safety-critical and dependable embedded systems calls for even cheaper, high performance platforms that allow flexibility and an efficient verification of safety and real-time requirements. To cope with the increasing complexity of interconnected functions and to reduce the cost and power consumption of the system, multicore systems are used to efficiently integrate different processing units in the same chip. Networks-on-chip (NoCs), as a modular interconnect, are used as a promising solution for such multiprocessor systems on chip (MPSoCs), due to their scalability and performance. For safety-critical systems, a major goal is the avoidance of hazards. For this, safety-critical systems are qualified or even certified to prove the correctness of the functioning under all possible cases. A predictable behaviour of the NoC can help to ease the qualification process of the system. To achieve the required predictability, designers have two classes of solutions: quality of service mechanisms and (formal) analysis. For mixed-criticality systems, isolation and analysis approaches must be combined to efficiently achieve the desired predictability. Traditional NoC analysis and architecture concepts tackle only a subpart of the challenges: they focus on either performance or predictability. Existing, predictable NoCs are deemed too expensive and inflexible to host a variety of applications with opposing constraints. And state-of-the-art analyses neglect certain platform properties to verify the behaviour. Together this leads to a high over-provisioning of the hardware resources as well as adverse impacts on system performance, and on the flexibility of the system. In this work we tackle these challenges and develop a predictable and runtime-adaptable NoC architecture that efficiently integrates mixed-critical applications with opposing constraints. Additionally, we present a modelling and analysis framework for NoCs that accounts for backpressure. This framework enables to evaluate the performance and reliability early at design time. Hence, the designer can assess multiple design decisions by using abstract models and formal approaches.Die Industrie der sicherheitskritischen und zuverlässigen eingebetteten Systeme verlangt nach noch günstigeren, leistungsfähigeren Plattformen, welche Flexibilität und eine effiziente Überprüfung der Sicherheits- und Echtzeitanforderungen ermöglichen. Um der zunehmenden Komplexität der zunehmend vernetzten Funktionen gerecht zu werden und die Kosten und den Stromverbrauch eines Systems zu reduzieren, werden Mehrkern-Systeme eingesetzt. On-Chip Netzwerke werden aufgrund ihrer Skalierbarkeit und Leistung als vielversprechende Lösung für solch Mehrkern-Systeme eingesetzt. Bei sicherheitskritischen Systemen ist die Vermeidung von Gefahren ein wesentliches Ziel. Dazu werden sicherheitskritische Systeme qualifiziert oder zertifiziert, um die Funktionsfähigkeit in allen möglichen Fällen nachzuweisen. Ein vorhersehbares Verhalten des on-Chip Netzwerks kann dabei helfen, den Qualifizierungsprozess des Systems zu erleichtern. Um die erforderliche Vorhersagbarkeit zu erreichen, gibt es zwei Klassen von Lösungen: Quality of Service Mechanismen und (formale) Analyse. Für Systeme mit gemischter Relevanz müssen Isolationsmechanismen und Analyseansätze kombiniert werden, um die gewünschte Vorhersagbarkeit effizient zu erreichen. Traditionelle Analyse- und Architekturkonzepte für on-Chip Netzwerke lösen nur einen Teil dieser Herausforderungen: sie konzentrieren sich entweder auf Leistung oder Vorhersagbarkeit. Existierende vorhersagbare on-Chip Netzwerke werden als zu teuer und unflexibel erachtet, um eine Vielzahl von Anwendungen mit gegensätzlichen Anforderungen zu integrieren. Und state-of-the-art Analysen vernachlässigen bzw. vereinfachen bestimmte Plattformeigenschaften, um das Verhalten überprüfen zu können. Dies führt zu einer hohen Überbereitstellung der Hardware-Ressourcen als auch zu negativen Auswirkungen auf die Systemleistung und auf die Flexibilität des Systems. In dieser Arbeit gehen wir auf diese Herausforderungen ein und entwickeln eine vorhersehbare und zur Laufzeit anpassbare Architektur für on-Chip Netzwerke, welche gemischt-kritische Anwendungen effizient integriert. Zusätzlich stellen wir ein Modellierungs- und Analyseframework für on-Chip Netzwerke vor, das den Paketrückstau berücksichtigt. Dieses Framework ermöglicht es, Designentscheidungen anhand abstrakter Modelle und formaler Ansätze frühzeitig beurteilen

    Zuverlässige und Energieeffiziente gemischt-kritische Echtzeit On-Chip Systeme

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    Multi- and many-core embedded systems are increasingly becoming the target for many applications that require high performance under varying conditions. A resulting challenge is the control, and reliable operation of such complex multiprocessing architectures under changes, e.g., high temperature and degradation. In mixed-criticality systems where many applications with varying criticalities are consolidated on the same execution platform, fundamental isolation requirements to guarantee non-interference of critical functions are crucially important. While Networks-on-Chip (NoCs) are the prevalent solution to provide scalable and efficient interconnects for the multiprocessing architectures, their associated energy consumption has immensely increased. Specifically, hard real-time NoCs must manifest limited energy consumption as thermal runaway in such a core shared resource jeopardizes the whole system guarantees. Thus, dynamic energy management of NoCs, as opposed to the related work static solutions, is highly necessary to save energy and decrease temperature, while preserving essential temporal requirements. In this thesis, we introduce a centralized management to provide energy-aware NoCs for hard real-time systems. The design relies on an energy control network, developed on top of an existing switch arbitration network to allow isolation between energy optimization and data transmission. The energy control layer includes local units called Power-Aware NoC controllers that dynamically optimize NoC energy depending on the global state and applications’ temporal requirements. Furthermore, to adapt to abnormal situations that might occur in the system due to degradation, we extend the concept of NoC energy control to include the entire system scope. That is, online resource management employing hierarchical control layers to treat system degradation (imminent core failures) is supported. The mechanism applies system reconfiguration that involves workload migration. For mixed-criticality systems, it allows flexible boundaries between safety-critical and non-critical subsystems to safely apply the reconfiguration, preserving fundamental safety requirements and temporal predictability. Simulation and formal analysis-based experiments on various realistic usecases and benchmarks are conducted showing significant improvements in NoC energy-savings and in treatment of system degradation for mixed-criticality systems improving dependability over the status quo.Eingebettete Many- und Multi-core-Systeme werden zunehmend das Ziel für Anwendungen, die hohe Anfordungen unter unterschiedlichen Bedinungen haben. Für solche hochkomplexed Multi-Prozessor-Systeme ist es eine grosse Herausforderung zuverlässigen Betrieb sicherzustellen, insbesondere wenn sich die Umgebungseinflüsse verändern. In Systeme mit gemischter Kritikalität, in denen viele Anwendungen mit unterschiedlicher Kritikalität auf derselben Ausführungsplattform bedient werden müssen, sind grundlegende Isolationsanforderungen zur Gewährleistung der Nichteinmischung kritischer Funktionen von entscheidender Bedeutung. Während On-Chip Netzwerke (NoCs) häufig als skalierbare Verbindung für die Multiprozessor-Architekturen eingesetzt werden, ist der damit verbundene Energieverbrauch immens gestiegen. Daher sind dynamische Plattformverwaltungen, im Gegensatz zu den statischen, zwingend notwendig, um ein System an die oben genannten Veränderungen anzupassen und gleichzeitig Timing zu gewährleisten. In dieser Arbeit entwickeln wir energieeffiziente NoCs für harte Echtzeitsysteme. Das Design basiert auf einem Energiekontrollnetzwerk, das auf einem bestehenden Switch-Arbitration-Netzwerk entwickelt wurde, um eine Isolierung zwischen Energieoptimierung und Datenübertragung zu ermöglichen. Die Energiesteuerungsschicht umfasst lokale Einheiten, die als Power-Aware NoC-Controllers bezeichnet werden und die die NoC-Energie in Abhängigkeit vom globalen Zustand und den zeitlichen Anforderungen der Anwendungen optimieren. Darüber hinaus wird das Konzept der NoC-Energiekontrolle zur Anpassung an Anomalien, die aufgrund von Abnutzung auftreten können, auf den gesamten Systemumfang ausgedehnt. Online- Ressourcenverwaltungen, die hierarchische Kontrollschichten zur Behandlung Abnutzung (drohender Kernausfälle) einsetzen, werden bereitgestellt. Bei Systemen mit gemischter Kritikalität erlaubt es flexible Grenzen zwischen sicherheitskritischen und unkritischen Subsystemen, um die Rekonfiguration sicher anzuwenden, wobei grundlegende Sicherheitsanforderungen erhalten bleiben und Timing Vorhersehbarkeit. Experimente werden auf der Basis von Simulationen und formalen Analysen zu verschiedenen realistischen Anwendungsfallen und Benchmarks durchgeführt, die signifikanten Verbesserungen bei On-Chip Netzwerke-Energieeinsparungen und bei der Behandlung von Abnutzung für Systeme mit gemischter Kritikalität zur Verbesserung die Systemstabilität gegenüber dem bisherigen Status quo zeigen

    Novel techniques in large scaleable ATM switches

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    Bibliography: p. 172-178.This dissertation explores the research area of large scale ATM switches. The requirements for an ATM switch are determined by overviewing the ATM network architecture. These requirements lead to the discussion of an abstract ATM switch which illustrates the components of an ATM switch that automatically scale with increasing switch size (the Input Modules and Output Modules) and those that do not (the Connection Admission Control and Switch Management systems as well as the Cell Switch Fabric). An architecture is suggested which may result in a scalable Switch Management and Connection Admission Control function. However, the main thrust of the dissertation is confined to the cell switch fabric. The fundamental mathematical limits of ATM switches and buffer placement is presented next emphasising the desirability of output buffering. This is followed by an overview of the possible routing strategies in a multi-stage interconnection network. A variety of space division switches are then considered which leads to a discussion of the hypercube fabric, (a novel switching technique). The hypercube fabric achieves good performance with an O(N.log₂N)²) scaling. The output module, resequencing, cell scheduling and output buffering technique is presented leading to a complete description of the proposed ATM switch. Various traffic models are used to quantify the switch's performance. These include a simple exponential inter-arrival time model, a locality of reference model and a self-similar, bursty, multiplexed Variable Bit Rate (VBR) model. FIFO queueing is simple to implement in an ATNI switch, however, more responsive queueing strategies can result in an improved performance. An associative memory is presented which allows the separate queues in the ATM switch to be effectively logically combined into a single FIFO queue. The associative memory is described in detail and its feasibility is shown by laying out the Integrated Circuit masks and performing an analogue simulation of the IC's performance is SPICE3. Although optimisations were required to the original design, the feasibility of the approach is shown with a 15Ƞs write time and a 160Ƞs read time for a 32 row, 8 priority bit, 10 routing bit version of the memory. This is achieved with 2µm technology, more advanced technologies may result in even better performance. The various traffic models and switch models are simulated in a number of runs. This shows the performance of the hypercube which outperforms a Clos network of equivalent technology and approaches the performance of an ideal reference fabric. The associative memory leverages a significant performance advantage in the hypercube network and a modest advantage in the Clos network. The performance of the switches is shown to degrade with increasing traffic density, increasing locality of reference, increasing variance in the cell rate and increasing burst length. Interestingly, the fabrics show no real degradation in response to increasing self similarity in the fabric. Lastly, the appendices present suggestions on how redundancy, reliability and multicasting can be achieved in the hypercube fabric. An overview of integrated circuits is provided. A brief description of commercial ATM switching products is given. Lastly, a road map to the simulation code is provided in the form of descriptions of the functionality found in all of the files within the source tree. This is intended to provide the starting ground for anyone wishing to modify or extend the simulation system developed for this thesis

    Revenue maximization problems in commercial data centers

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    PhD ThesisAs IT systems are becoming more important everyday, one of the main concerns is that users may face major problems and eventually incur major costs if computing systems do not meet the expected performance requirements: customers expect reliability and performance guarantees, while underperforming systems loose revenues. Even with the adoption of data centers as the hub of IT organizations and provider of business efficiencies the problems are not over because it is extremely difficult for service providers to meet the promised performance guarantees in the face of unpredictable demand. One possible approach is the adoption of Service Level Agreements (SLAs), contracts that specify a level of performance that must be met and compensations in case of failure. In this thesis I will address some of the performance problems arising when IT companies sell the service of running ‘jobs’ subject to Quality of Service (QoS) constraints. In particular, the aim is to improve the efficiency of service provisioning systems by allowing them to adapt to changing demand conditions. First, I will define the problem in terms of an utility function to maximize. Two different models are analyzed, one for single jobs and the other useful to deal with session-based traffic. Then, I will introduce an autonomic model for service provision. The architecture consists of a set of hosted applications that share a certain number of servers. The system collects demand and performance statistics and estimates traffic parameters. These estimates are used by management policies which implement dynamic resource allocation and admission algorithms. Results from a number of experiments show that the performance of these heuristics is close to optimal.QoSP (Quality of Service Provisioning)British Teleco

    Reliable, Context-Aware and Energy-Efficient Architecture for Wireless Body Area Networks in Sports Applications

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    RÉSUMÉ Un Réseau Corporel Sans Fil (RCSF, Wireless Body Area Network en anglais ou WBAN) permet de collecter de l'information à partir de capteurs corporels. Cette information est envoyée à un hub qui la transforme et qui peut aussi effectuer d'autres fonctions comme gérer des événements corporels, fusionner les données à partir des capteurs, percevoir d’autres paramètres, exécuter les fonctions d’une interface d’utilisateur, et faire un lien vers des infrastructures de plus haut niveau et d’autres parties prenantes. La réduction de la consommation d'énergie d’un RCSF est un des aspects les plus importants qui doit être amélioré lors de sa conception. Cet aspect peut impliquer le développement de protocoles de Contrôles d'Accès au Support (CAS, Media Access Control en anglais ou MAC), protocoles de transport et de routage plus efficients. Le contrôle de la congestion est un autre des facteurs les plus importants dans la conception d’un RCSF, parce que la congestion influe directement sur la Qualité De Service (QDS, Quality of Service en anglais ou QoS) et l’efficience en énergie du réseau. La congestion dans un RCSF peut produire une grande perte de paquets et une haute consommation d’énergie. La QDS est directement impactée par la perte de paquets. L’implémentation de mesures additionnelles est nécessaire pour atténuer l’impact sur la communication des RCSF. Les protocoles de CAS pour RCSF devraient permettre aux capteurs corporels d’accéder rapidement au canal de communication et d’envoyer les données au hub, surtout pour les événements urgents tout en réduisant la consommation d’énergie. Les protocoles de transport pour RCSF doivent fournir de la fiabilité bout-à-bout et de la QDS pour tout le réseau. Cette tâche peut être accomplie par la réduction du ratio de perte de paquets (Packet Loss Ratio en anglais ou PLR) et de la latence tout en gardant l'équité et la faible consommation d'énergie entre les noeuds. Le standard IEEE 802.15.6 suggère un protocole de CAS qui est destiné à être applicable à tous les types de RCSF; toutefois, ce protocole peut être amélioré pour les RCSF utilisés dans le domaine du sport, où la gestion du trafic pourrait être différente d’autres réseaux. Le standard IEEE 802.15.6 comprend la QDS, mais cela ne suggère aucun protocole de transport ou système de contrôle du débit. Le but principal de ce projet de recherche est de concevoir une architecture pour RCSF en trois phases : (i) Conception d’un mécanisme sensible au contexte et efficient en énergie pour fournir une QDS aux RCSF; (ii) Conception d’un mécanisme fiable et efficient en énergie pour fournir une récupération des paquets perdus et de l’équité dans les RCSF; et (iii) Conception d’un système de contrôle du débit sensible au contexte pour fournir un contrôle de congestion aux RCSF. Finalement, ce projet de recherche propose une architecture fiable, sensible au contexte et efficiente en énergie pour RCSF utilisés dans le domaine du sport. Cette architecture fait face à quatre défis : l'efficacité de l'énergie, la sensibilité au contexte, la qualité de service et la fiabilité. La mise en place de cette solution aidera à l’amélioration des compétences, de la performance, de l’endurance et des protocoles d’entraînement des athlètes, ainsi qu’à la détection des points faibles. Cette solution pourrait être prolongée à l’amélioration de la qualité de vie des enfants, des personnes malades ou âgées, ou encore aux domaines militaires, de la sécurité et du divertissement. L’évaluation des protocoles et schémas proposés a été faite par simulations programmées avec le simulateur OMNeT++ et le système Castalia. Premièrement, le protocole de CAS proposé a été comparé avec les protocoles de CAS suivants : IEEE 802.15.6, IEEE 802.15.4 et T-MAC (Timeout MAC). Deuxièmement, le protocole de CAS proposé a été comparé avec le standard IEEE 802.15.6 avec et sans l’utilisation du protocole de transport proposé. Finalement, le protocole de CAS proposé et le standard IEEE 802.15.6 ont été comparés avec et sans l’utilisation du système de contrôle du débit proposé. Le protocole de CAS proposé surpasse les protocoles de CAS IEEE 802.15.6, IEEE 802.15.4 et T-MAC dans le pourcentage de pertes de paquets d’urgence et normaux, l’efficacité en énergie, et la latence du trafic d’urgence et du trafic normal. Le protocole de CAS proposé utilisé avec le protocole du transport proposé surpasse la performance du standard IEEE 802.15.6 dans le pourcentage de perte de paquets avec ou sans trafic d’urgence, l’efficacité en énergie, et la latence du trafic normal. Le système de contrôle du débit proposé a amélioré la performance du protocole de CAS proposé et du standard IEEE 802.15.6 dans le pourcentage de perte de paquets avec ou sans trafic d’urgence, l’efficacité en énergie, et la latence du trafic d’urgence.----------ABSTRACT Information collected from body sensors in a Wireless Body Area Network (WBAN) is sent to a hub or coordinator which processes the information and can also perform other functions such as managing body events, merging data from sensors, sensing other parameters, performing the functions of a user interface and bridging the WBAN to higher-level infrastructure and other stakeholders. The reduction of the power consumption of a WBAN is one of the most important aspects to be improved when designing a WBAN. This challenge might imply the development of more efficient Medium Access Control (MAC), transport and routing protocols. Congestion control is another of the most important factors when a WBAN is designed, due to its direct impact in the Quality of Service (QoS) and the energy efficiency of the network. The presence of congestion in a WBAN can produce a big packet loss and high energy consumption. The QoS is also impacted directly by the packet loss. The implementation of additional measures is necessary to mitigate the impact on WBAN communications. The MAC protocols for WBANs should allow body sensors to get quick access to the channel and send data to the hub, especially in emergency events while reducing the power consumption. The transport protocols for WBANs must provide end-to-end reliability and QoS for the whole network. This task can be accomplished through the reduction of both the Packet Loss Ratio (PLR) and the latency while keeping fairness and low power consumption between nodes. The IEEE 802.15.6 standard suggests a MAC protocol which is intended to be applicable for all kinds of WBANs. Nonetheless, it could be improved for sports WBANs where the traffic-types handling could be different from other networks. The IEEE 802.15.6 standard supports QoS, but it does not suggest any transport protocol or rate control scheme. The main objective of this research project is to design an architecture for WBANs in three phases: (i) Designing a context-aware and energy-efficient mechanism for providing QoS in WBANs; (ii) Designing a reliable and energy-efficient mechanism to provide packet loss recovery and fairness in WBANs; and (iii) Designing a context-aware rate control scheme to provide congestion control in WBANs. Finally, this research project proposes a reliable, context-aware and energy-efficient architecture for WBANs used in sports applications, facing four challenges: energy efficiency, context awareness, quality of service and reliability. The benefits of this solution will help to improve skills, performance, endurance and training protocols of athletes, and deficiency detection. Also, it could be extended to enhance the quality of life of children, ill and elderly people, and to security, military and entertainment fields. The evaluation of the proposed protocols and schemes was made through simulations programed in the OMNeT++ simulator and the Castalia framework. First, the proposed MAC protocol was compared against the IEEE 802.15.6 MAC protocol, the IEEE 802.15.4 MAC protocol and the T-MAC (Timeout MAC) protocol. Second, the proposed MAC protocol was compared with the IEEE 802.15.6 standard with and without the use of the proposed transport protocol. Finally, both the proposed MAC protocol and the IEEE 802.15.6 standard were compared with and without the use of the proposed rate control scheme. The proposed MAC protocol outperforms the IEEE 802.15.6 MAC protocol, the IEEE 802.15.4 MAC protocol and the T-MAC protocol in the percentage of emergency and normal packet loss, the energy effectiveness, and the latency of emergency and normal traffic. The proposed MAC protocol working along with the proposed transport protocol outperforms the IEEE 802.15.6 standard in the percentage of the packet loss with or without emergency traffic, the energy effectiveness, and the latency of normal traffic. The proposed rate control scheme improved the performance of both the proposed MAC protocol and the IEEE 802.15.6 standard in the percentage of the packet loss with or without emergency traffic, the energy effectiveness and the latency of emergency traffic
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