1,042 research outputs found

    HDL-based Synthesis of Reversible Circuits : A Scalable Design Approach

    Get PDF
    Reversible computing is a promising research field due to its applications in several emerging technologies. Accordingly, several approaches for the design of reversible circuits have been introduced. Hardware Description Languages approach scales better than other methodologies, however, its main drawback is substantial amounts of additional circuit lines. This dissertation is an important step towards an elaborated scalable design flow of reversible circuits. In which, HDL-based design of reversible circuit is optimised, with line-awareness considered as the main objective. A line-aware programming style for a dedicated reversible hardware description language SyReC is proposed. Another contribution is a line-aware computation of HDL expressions. Reversible circuits' synthesis from a conventional hardware description language (VHDL) is examined. Finally, syntactical extensions to the dedicated hardware description language SyReC are suggested

    Fault tolerant resource estimation of quantum random-access memories

    Full text link
    Quantum random-access look-up of a string of classical bits is a necessary ingredient in several important quantum algorithms. In some cases, the cost of such quantum random-access memory (qRAM) is the limiting factor in the implementation of the algorithm. In this paper we study the cost of fault-tolerantly implementing a qRAM. We construct generic families of circuits which function as a qRAM, and analyze their resource costs when embedded in a surface code.Comment: 17 pages, 12 figures. Code repository available in reference

    The role of multiplicative complexity in compiling Low T-count Oracle circuits

    Get PDF
    We present a constructive method to create quantum circuits that implement oracles |x〉|y〉|0〉 k →|x〉|y⊕f(x)〉|0〉 k for n-variable Boolean functions f with low T-count. In our method f is given as a 2-regular Boolean logic network over the gate basis {∧, ⊕, 1}. Our construction leads to circuits with a T-count that is at most four times the number of AND nodes in the network. In addition, we propose a SAT-based method that allows us to trade qubits for T gates, and explore the space/complexity trade-off of quantum circuits. Our constructive method suggests a new upper bound for the number of T gates and ancilla qubits based on the multiplicative complexity c∧(f) of the oracle function f, which is the minimum number of AND gates that is required to realize f over the gate basis {∧, ⊕, 1}. There exists a quantum circuit computing f with at most 4c∧(f)T gates using k=c∧(f) ancillae. Results known for the multiplicative complexity of Boolean functions can be transferred. We verify our method by comparing it to different state-of-the-art compilers. Finally, we present our synthesis results for Boolean functions used in quantum cryptoanalysis

    Power Reductions with Energy Recovery Using Resonant Topologies

    Get PDF
    The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

    Minimization of lines in reversible circuits

    Get PDF
    Reversible computing has been theoretically shown to be an efficient approach over conventional computing due to the property of virtually zero power dissipation. A major concern in reversible circuits is the number of circuit lines or qubits which are a limited resource. In this thesis we explore the line reduction problem using a decision diagram based synthesis approach and introduce a line reduction algorithm— Minimization of lines using Ordered Kronecker Functional Decision Diagrams (MOKFDD). The algorithm uses a new sub-circuit for a positive Davio node structure in addition to the existing node structures. We also present a shared node ordering for OKFDDs. OKFDDs are a combination of OBDDs and OFDDs. The experimental results shows that the number of circuit lines and quantum cost can be reduced with our proposed approach.NSER
    • …
    corecore