Track Assignment Considering Crosstalk-Induced Performance Degradation

Track assignment is a critical step between global routing and detailed routing in modern VLSI chip designs. It greatly affects some very important design characteristics, such as routability, via usage and timing performance. Crosstalk, which is largely decided by wire adjacency, has significant impact on interconnect delay and circuit performance. Therefore, the amount of crosstalk should be restrained in order to satisfy timing constraints. In this work, a track assignment approach is proposed to control crosstalk-induced performance degradation. The problem is formulated as a Traveling Salesman Problem (TSP) and solved by a graph-based heuristic. The proposed approach is implemented and tested on benchmark circuits from the ISPD2011 contest and the experimental results are quite promising

On Co-Optimization Of Constrained Satisfiability Problems For Hardware Software Applications

Manufacturing technology has permitted an exponential growth in transistor count and density. However, making efficient use of the available transistors in the design has become exceedingly difficult. Standard design flow involves synthesis, verification, placement and routing followed by final tape out of the design. Due to the presence of various undesirable effects like capacitive crosstalk, supply noise, high temperatures, etc., verification/validation of the design has become a challenging problem. Therefore, having a good design convergence may not be possible within the target time, due to a need for a large number of design iterations. Capacitive crosstalk is one of the major causes of design convergence problems in deep sub-micron era. With scaling, the number of crosstalk violations has been increasing because of reduced inter-wire distances. Consequently only the most severe crosstalk faults are fixed pre-silicon while the rest are tested post-silicon. Testing for capacitive crosstalk involves generation of input patterns which can be applied post-silicon to the integrated circuit and comparison of the output response. These patterns are generated at the gate/ Register Transfer Level (RTL) of abstraction using Automatic Test Pattern Generation (ATPG) tools. In this dissertation, anInteger Linear Programming (ILP) based ATPG technique for maximizing crosstalk induced delay increase at the victim net, for multiple aggressor crosstalk faults, is presented. Moreover, various solutions for pattern generation considering both zero as well as unit delay models is also proposed. With voltage scaling, power supply switching noise has become one of the leading causes of signal integrity related failures in deep sub-micron designs. Hence, during power supply network design and analysis of power supply switching noise, computation of peak supply current is an essential step. Traditional peak current estimation approaches involve addition of peak current associated with all the CMOS gates which are switching in a combinational circuit. Consequently, this approach does not take the Boolean and temporal relationships of the circuit into account. This work presents an ILP based technique for generation of an input pattern pair which maximizes switching supply currents for a combinational circuit in the presence of integer gate delays. The input pattern pair generated using the above approach can be applied post-silicon for power droop testing. With high level of integration, Multi-Processor Systems on Chip (MPSoC) feature multiple processor cores and accelerators on the same die, so as to exploit the instruction level parallelism in the application. For hardware-software co-design, application programming model is based on a Task Graph, which represents task dependencies and execution/transfer times for various threads and processes within an application. Mapping an application to an MPSoC traditionally involves representing it in the form of a task graph and employing static scheduling in order to minimize the schedule length. Dynamic system behavior is not taken into consideration during static scheduling, while dynamic scheduling requires the knowledge of task graph at runtime. A run-time task graph extraction heuristic to facilitate dynamic scheduling is also presented here. A novel game theory based approach uses this extracted task graph to perform run-time scheduling in order to minimize total schedule length. With increase in transistor density, power density has gone up substantially. This has lead to generation of regions with very high temperature called Hotspots. Hotspots lead to reliability and performance issues and affect design convergence. In current generation Integrated Circuits (ICs) temperature is controlled by reducing power dissipation using Dynamic Thermal Management (DTM) techniques like frequency and/or voltage scaling. These techniques are reactive in nature and have detrimental effects on performance. Here, a look-ahead based task migration technique is proposed, in order to utilize the multitude of cores available in an MPSoC to eliminate thermal emergencies. Our technique is based on temperature prediction, leveraging upon a novel wavelet based thermal modeling approach. Hence, this work addresses several optimization problems that can be reduced to constrained max-satisfiability, involving integer as well as Boolean constraints in hardware and software domains. Moreover, it provides domain specific heuristic solutions for each of them

Silicon Photomultipliers in Particle and Nuclear Physics

Following first large-scale applications in highly granular calorimeters and in neutrino detectors, Silicon Photomultipliers have seen a wide adoption in accelerator-based particle and nuclear physics experiments. Today, they are used for a wide range of different particle detector types, ranging from calorimeters and trackers to particle identification and veto detectors, large volume detectors for neutrino physics and timing systems. This article reviews the current state and expected evolution of these applications, highlighting strengths and limitation of SiPMs and the corresponding design choices in the respective contexts. General trends and adopted technical solutions in the applications are discussed.Comment: 17 pages, 18 figures, review paper published in Nuclear Instruments and Methods A; v2 correcting a missing figure link in tex

Crosstalk aware light-path selection in optical wdm/dwdm networks

Physical layer impairments are the major limitation for the high speed optical WDM/DWDM networks. They significantly affect the signal quality resulting poor quality of transmission which is normally expressed in terms of bit-error rate. To cope of with the future demand, increase in the no of channels and data speed further enhances these impairments. Hence new techniques are needed, which mitigate these impairments and ensure a better quality of transmission. Among the physical layer impairments we have studied the impact of in-band crosstalk on transmission performance of a transparent WDM/DWDM network. Error probabilities and power penalties produced by crosstalk are also investigated. As traditional RWA scheme pays a little regard to the physical layer impairments and cannot provide optimized network performance in practical networks, we have proposed a novel BER constrained, FWM aware RWA algorithm. The performance of the proposed algorithm is demonstrated through simulation and the results show that our algorithm not only gives a guaranteed quality of transmission but also improves the network performance in terms of blocking probability

Layout optimization in ultra deep submicron VLSI design

As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design. The place-and-route stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed routing. Among them, layer/track assignment assigns major trunks of wire segments to specific layers/tracks in order to guide the underlying detailed router. In this dissertation, we have proposed techniques to handle coupling capacitance at the layer/track assignment stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering Change Order) placement stage, respectively. More specifically, at layer assignment, we have proposed an improved probabilistic model to quickly estimate the amount of coupling capacitance for timing optimization. Antenna effects are also handled at layer assignment through a linear-time tree partitioning algorithm. At the track assignment stage, timing is further optimized using a graph based technique. In addition, we have proposed a novel gate splitting methodology to reduce delay variation in the ECO placement considering spatial correlations. Experimental results on benchmark circuits showed the effectiveness of our approaches

Improved Physical Design for Manufacturing Awareness and Advanced VLSI

Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research

Design, monitoring and performance evaluation of high capacity optical networks

Premi Extraordinari de Doctorat, promoció 2018-2019. Àmbit de les TICInternet traffic is expected to keep increasing exponentially due to the emergence of a vast number of innovative online services and applications. Optical networks, which are the cornerstone of the underlying Internet infrastructure, have been continuously evolving to carry the ever-increasing traffic in a more flexible, cost-effective, and intelligent way. Having these three targets in mind, this PhD thesis focuses on two general areas for the performance improvement and the evolution of optical networks: i) introducing further cognition to the optical layer, and ii) introducing new networking solutions revolutionizing the optical transport infrastructure. In the first part, we present novel failure detection and identification solutions in the optical layer utilizing the optical spectrum traces captured by cost-effective coarse-granular Optical Spectrum Analyzers (OSA). We demonstrate the effectiveness of the developed solutions for detecting and identifying filter-related failures in the context of Spectrum-Switched Optical Networks (SSON), as well as transmitter-related laser failures in Filter-less Optical Networks (FON). In addition, at the subsystem level we propose an Autonomic Transmission Agent (ATA), which triggers local or remote transceiver reconfiguration by predicting Bit-Error-Rate (BER) degradation by monitoring State-of-Polarization (SOP) data obtained by coherent receivers. I have developed solutions to push further the performance of the currently deployed optical networks through reducing the margins and introducing intelligence to better manage their resources. However, it is expected that the spectral efficiency of the current standard Single-Mode Fiber (SMF) based optical network approaches the Shannon capacity limits in the near future, and therefore, a new paradigm is required to keep with the pace of the current huge traffic increase. In this regard, Space Division Multiplexing (SDM) is proposed as the ultimate solution to address the looming capacity crunch with a reduced cost-per-bit delivered to the end-users. I devote the second part of this thesis to investigate different flavors of SDM based optical networks with the aim of finding the best compromise for the realization of a spectrally and spatially flexible optical network. SDM-based optical networks can be deployed over various types of transmission media. Additionally, due to the extra dimension (i.e., space) introduced in SDM networks, optical switching nodes can support wavelength granularity, space granularity, or a combination of both. In this thesis, we evaluate the impact of various spectral and spatial switching granularities on the performance of SDM-based optical networks serving different profiles of traffic with the aim of understanding the impact of switching constraints on the overall network performance. In this regard, we consider two different generations of wavelength selective switches (WSS) to reflect the technology limitations on the performance of SDM networks. In addition, we present different designs of colorless direction-less, and Colorless Directionless Contention-less (CDC) Reconfigurable Optical Add/Drop Multiplexers (ROADM) realizing SDM switching schemes and compare their performance in terms of complexity and implementation cost. Furthermore, with the aim of revealing the benefits and drawbacks of SDM networks over different types of transmission media, we preset a QoT-aware network planning toolbox and perform comparative performance analysis among SDM network based on various types of transmission media. We also analyze the power consumption of Multiple-Input Multiple-Output (MIMO) Digital Signal Processing (DSP) units of transceivers operating over three different types of transmission media. The results obtained in the second part of the thesis provide a comprehensive outlook to different realizations of SDM-based optical networks and showcases the benefits and drawbacks of different SDM realizations.Se espera que el tráfico de Internet siga aumentando exponencialmente debido a la continua aparición de gran cantidad de aplicaciones innovadoras. Las redes ópticas, que son la piedra angular de la infraestructura de Internet, han evolucionado continuamente para transportar el tráfico cada vez mayor de una manera más flexible, rentable e inteligente. Teniendo en cuenta estos tres objetivos, esta tesis doctoral se centra en dos áreas cruciales para la mejora del rendimiento y la evolución de las redes ópticas: i) introducción de funcionalidades cognitivas en la capa óptica, y ii) introducción de nuevas estructuras de red que revolucionarán el transporte óptico. En la primera parte, se presentan soluciones novedosas de detección e identificación de fallos en la capa óptica que utilizan trazas de espectro óptico obtenidas mediante analizadores de espectros ópticos (OSA) de baja resolución (y por tanto de coste reducido). Se demuestra la efectividad de las soluciones desarrolladas para detectar e identificar fallos derivados del filtrado imperfecto en las redes ópticas de conmutación de espectro (SSON), así como fallos relacionados con el láser transmisor en redes ópticas sin filtro (FON). Además, a nivel de subsistema, se propone un Agente de Transmisión Autónomo (ATA), que activa la reconfiguración del transceptor local o remoto al predecir la degradación de la Tasa de Error por Bits (BER), monitorizando el Estado de Polarización (SOP) de la señal recibida en un receptor coherente. Se han desarrollado soluciones para incrementar el rendimiento de las redes ópticas mediante la reducción de los márgenes y la introducción de inteligencia en la administración de los recursos de la red. Sin embargo, se espera que la eficiencia espectral de las redes ópticas basadas en fibras monomodo (SMF) se acerque al límite de capacidad de Shannon en un futuro próximo, y por tanto, se requiere un nuevo paradigma que permita mantener el crecimiento necesario para soportar el futuro aumento del tráfico. En este sentido, se propone el Multiplexado por División Espacial (SDM) como la solución que permita la continua reducción del coste por bit transmitido ante ése esperado crecimiento del tráfico. En la segunda parte de esta tesis se investigan diferentes tipos de redes ópticas basadas en SDM con el objetivo de encontrar soluciones para la realización de redes ópticas espectral y espacialmente flexibles. Las redes ópticas basadas en SDM se pueden implementar utilizando diversos tipos de medios de transmisión. Además, debido a la dimensión adicional (el espacio) introducida en las redes SDM, los nodos de conmutación óptica pueden conmutar longitudes de onda, fibras o una combinación de ambas. Se evalúa el impacto de la conmutación espectral y espacial en el rendimiento de las redes SDM bajo diferentes perfiles de tráfico ofrecido, con el objetivo de comprender el impacto de las restricciones de conmutación en el rendimiento de la red. En este sentido, se consideran dos generaciones diferentes de conmutadores selectivos de longitud de onda (WSS) para reflejar las limitaciones de la tecnología en el rendimiento de las redes SDM. Además, se presentan diferentes diseños de ROADM, independientes de la longitud de onda, de la dirección, y sin contención (CDC) utilizados para la conmutación SDM, y se compara su rendimiento en términos de complejidad y coste. Además, con el objetivo de cuantificar los beneficios e inconvenientes de las redes SDM, se ha generado una herramienta de planificación de red que prevé la QoT usando diferentes tipos de fibras. También se analiza el consumo de energía de las unidades DSP de los transceptores MIMO operando en redes SDM con tres tipos diferentes de medios de transmisión. Los resultados obtenidos en esta segunda parte de la tesis proporcionan una perspectiva integral de las redes SDM y muestran los beneficios e inconvenientes de sus diferentes implementacionesAward-winningPostprint (published version

Shuttle/TDRSS Ku-band downlink study

Assessing the adequacy of the baseline signal design approach, developing performance specifications for the return link hardware, and performing detailed design and parameter optimization tasks was accomplished by completing five specific study tasks. The results of these tasks show that the basic signal structure design is sound and that the goals can be met. Constraints placed on return link hardware by this structure allow reasonable specifications to be written so that no extreme technical risk areas in equipment design are foreseen. A third channel can be added to the PM mode without seriously degrading the other services. The feasibility of using only a PM mode was shown to exist, however, this will require use of some digital TV transmission techniques. Each task and its results are summarized

Acoustically driven arrayed waveguide grating

We demonstrate compact tunable phased-array wavelength-division multiplexers driven by surface acoustic waves (SAWs) in the low GHz range. The devices comprise two couplers, which respectively split and combine the optical signal, linked by an array of single-mode waveguides (WGs). Two different layouts are presented, in which multi-mode interference couplers or free propagating regions were separately employed as couplers. The multiplexers operate on five equally distributed wavelength channels, with a spectral separation of 2 nm. A standing SAW modulates the refractive index of the arrayed WGs. Each wavelength component periodically switches paths between the output channel previously asigned by the design and the adjacent channels, at a fixed applied acoustic power. The devices were monolithically fabricated on (Al,Ga)As. A good agreement between theory and experiment is achieved