Introduction to topological quantum computation with non-Abelian anyons

Topological quantum computers promise a fault tolerant means to perform quantum computation. Topological quantum computers use particles with exotic exchange statistics called non-Abelian anyons, and the simplest anyon model which allows for universal quantum computation by particle exchange or braiding alone is the Fibonacci anyon model. One classically hard problem that can be solved efficiently using quantum computation is finding the value of the Jones polynomial of knots at roots of unity. We aim to provide a pedagogical, self-contained, review of topological quantum computation with Fibonacci anyons, from the braiding statistics and matrices to the layout of such a computer and the compiling of braids to perform specific operations. Then we use a simulation of a topological quantum computer to explicitly demonstrate a quantum computation using Fibonacci anyons, evaluating the Jones polynomial of a selection of simple knots. In addition to simulating a modular circuit-style quantum algorithm, we also show how the magnitude of the Jones polynomial at specific points could be obtained exactly using Fibonacci or Ising anyons. Such an exact algorithm seems ideally suited for a proof of concept demonstration of a topological quantum computer.Comment: 51 pages, 51 figure

Energy analysis and optimisation techniques for automatically synthesised coprocessors

The primary outcome of this research project is the development of a methodology enabling fast automated early-stage power and energy analysis of configurable processors for system-on-chip platforms. Such capability is essential to the process of selecting energy efficient processors during design-space exploration, when potential savings are highest. This has been achieved by developing dynamic and static energy consumption models for the constituent blocks within the processors. Several optimisations have been identified, specifically targeting the most significant blocks in terms of energy consumption. Instruction encoding mechanism reduces both the energy and area requirements of the instruction cache; modifications to the multiplier unit reduce energy consumption during inactive cycles. Both techniques are demonstrated to offer substantial energy savings. The aforementioned techniques have undergone detailed evaluation and, based on the positive outcomes obtained, have been incorporated into Cascade, a system-on-chip coprocessor synthesis tool developed by Critical Blue, to provide automated analysis and optimisation of processor energy requirements. This thesis details the process of identifying and examining each method, along with the results obtained. Finally, a case study demonstrates the benefits of the developed functionality, from the perspective of someone using Cascade to automate the creation of an energy-efficient configurable processor for system-on-chip platforms

An automated OpenCL FPGA compilation framework targeting a configurable, VLIW chip multiprocessor

Modern system-on-chips augment their baseline CPU with coprocessors and accelerators to increase overall computational capacity and power efficiency, and thus have evolved into heterogeneous systems. Several languages have been developed to enable this paradigm shift, including CUDA and OpenCL. This thesis discusses a unified compilation environment to enable heterogeneous system design through the use of OpenCL and a customised VLIW chip multiprocessor (CMP) architecture, known as the LE1. An LLVM compilation framework was researched and a prototype developed to enable the execution of OpenCL applications on the LE1 CPU. The framework fully automates the compilation flow and supports work-item coalescing to better utilise the CPU cores and alleviate the effects of thread divergence. This thesis discusses in detail both the software stack and target hardware architecture and evaluates the scalability of the proposed framework on a highly precise cycle-accurate simulator. This is achieved through the execution of 12 benchmarks across 240 different machine configurations, as well as further results utilising an incomplete development branch of the compiler. It is shown that the problems generally scale well with the LE1 architecture, up to eight cores, when the memory system becomes a serious bottleneck. Results demonstrate superlinear performance on certain benchmarks (x9 for the bitonic sort benchmark with 8 dual-issue cores) with further improvements from compiler optimisations (x14 for bitonic with the same configuration

Power extraction circuits for piezoelectric energy harvesters and time series data in water supply systems

This thesis investigates two fundamental technological challenges that prevent water utilities from deploying infrastructure monitoring apparatus with high spatial and temporal resolution: providing sufficient power for sensor nodes by increasing the power output from a vibration-driven energy harvester based on piezoelectric transduction, and the processing and storage of large volumes of data resulting from the increased level of pressure and flow rate monitoring. Piezoelectric energy harvesting from flow-induced vibrations within a water main represents a potential source of power to supply a sensor node capable of taking high- frequency measurements. A main factor limiting the amount of power from a piezoelectric device is the damping force that can be achieved. Electronic interface circuits can modify this damping in order to increase the power output to a reasonable level. A unified analytical framework was developed to compare circuits able to do this in terms of their power output. A new circuit is presented that out-performs existing circuits by a factor of 2, which is verified experimentally. The second problem concerns the management of large data sets arising from resolving challenges with the provision of power to sensor devices. The ability to process large data volumes is limited by the throughput of storage devices. For scientists to execute queries in a timely manner, query execution must be performant. The large volume of data that must be gathered to extract information from historic trends mandates a scalable approach. A scalable, durable storage and query execution framework is presented that is able to significantly improve the execution time of user-defined queries. A prototype database was implemented and validated on a cluster of commodity servers using live data gathered from a London pumping station and transmission mains. Benchmark results and reliability tests are included that demonstrate a significant improvement in performance over a traditional database architecture for a range of frequently-used operations, with many queries returning results near-instantaneously

A Novel DC-DC Converter for Photovoltaic Applications

Growing concerns about climate change have led to the world experiencing an unprecedented push towards renewable energy. Economic drivers and government policies mean that small, distributed forms of generation, like solar photovoltaics, will play a large role in our transition to a clean energy future. In this thesis, a novel DC-DC converter known as the Coupled Inductors Combined Cuk-SEPIC' (CI-CCS) converter is explored, which is particularly attractive for these photovoltaic applications. A topological modification is investigated which provides several benefits, including increased power density, efficiency, and operational advantages for solar energy conversion. The converter, which is based on the combination of the Cuk and SEPIC converters, provides a bipolar output (i.e. both positive and negative voltages). This converter also offers both step-up and step-down capabilities with a continuous input current, and uses only a single, ground-referenced switching device. A significant enhancement to this converter is proposed: magnetic coupling of the converter's three inductors. This can substantially reduce the CI-CCS converter's input current ripple - an important benefit for maximum power point tracking (MPPT) in photovoltaic applications. The effect of this coupling is examined theoretically, and optimisations are performed - both analytically and in simulations - to inform the design of a 4 kW prototype CI-CCS converter, switched at a high frequency (100 kHz) with a silicon carbide (SiC) MOSFET. Simulation and experimental results are then presented to demonstrate the CI-CCS converter's operation and highlight the benefits of coupling its inductors. An efficiency analysis is also undertaken and its sources of losses are quantified. The converter is subsequently integrated into a domestic photovoltaic system to provide a practical demonstration of its suitability for such applications. MPPT is integrated into the CI-CCS DC-DC converter, and a combined half bridge/T-type converter is developed and paired with the CI-CCS converter to form an entirely transformerless single-phase solar energy conversion system. The combination of the CI-CCS converter's bipolar DC output with the combined half bridge/T-type converter's bipolar DC input allows grounding at both the photovoltaic panels and the AC grid's neutral point. This eliminates high frequency common mode voltages from the PV array, which in turn prevents leakage currents.The entire system can be operated in grid-connected mode - where the objective is to maximise power extracted from the photovoltaic system, and is demonstrated in stand-alone mode - where the objective is to match solar generation with the load's power demands.General Sir John Monash Foundation, Origin Foundation, Cambridge Trust, Cambridge Australia Scholarships, Mr Charles Alle