47 research outputs found

    A Polyphase Multipath Technique for Software-Defined Radio Transmitters

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    Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-mum CMOS, aiming at a software-defined radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Omega load (2.54 Vpp-diff voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixer

    Techniques for Wideband All Digital Polar Transmission

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    abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

    Transmissores reconfiguráveis para rádios definidos por software

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    Doutoramento em Engenharia ElectrotécnicaFlexible radio transmitters based on the Software-Defined Radio (SDR) concept are gaining an increased research importance due to the unparalleled proliferation of new wireless standards operating at different frequencies, using dissimilar coding and modulation schemes, and targeted for different ends. In this new wireless communications paradigm, the physical layer of the radio transmitter must be able to support the simultaneous transmission of multi-band, multi-rate, multi-standard signals, which in practice is very hard or very inefficient to implement using conventional approaches. Nevertheless, the last developments in this field include novel all-digital transmitter architectures where the radio datapath is digital from the baseband up to the RF stage. Such concept has inherent high flexibility and poses an important step towards the development of SDR-based transmitters. However, the truth is that implementing such radio for a real world communications scenario is a challenging task, where a few key limitations are still preventing a wider adoption of this concept. This thesis aims exactly to address some of these limitations by proposing and implementing innovative all-digital transmitter architectures with inherent higher flexibility and integration, and where improving important figures of merit, such as coding efficiency, signal-to-noise ratio, usable bandwidth and in-band and out-of-band noise will also be addressed. In the first part of this thesis, the concept of transmitting RF data using an entirely digital approach based on pulsed modulation is introduced. A comparison between several implementation technologies is also presented, allowing to state that FPGAs provide an interesting compromise between performance, power efficiency and flexibility, thus making them an interesting choice as an enabling technology for pulse-based all-digital transmitters. Following this discussion, the fundamental concepts inherent to pulsed modulators, its key advantages, main limitations and typical enhancements suitable for all-digital transmitters are also presented. The recent advances regarding the two most common classes of pulse modulated transmitters, namely the RF and the baseband-level are introduced, along with several examples of state-of-the-art architectures found on the literature. The core of this dissertation containing the main developments achieved during this PhD work is then presented and discussed. The first key contribution to the state-of-the-art presented here consists in the development of a novel ΣΔ-based all-digital transmitter architecture capable of multiband and multi-standard data transmission in a very flexible and integrated way, where the pulsed RF output operating in the microwave frequency range is generated inside a single FPGA device. A fundamental contribution regarding the simultaneous transmission of multiple RF signals is then introduced by presenting and describing novel all-digital transmitter architectures that take advantage of multi-gigabit data serializers available on current high-end FPGAs in order to transmit in a time-interleaved approach multiple independent RF carriers. Further improvements in this design approach allowed to provide a two-stage up-conversion transmitter architecture enabling the fine frequency tuning of concurrent multichannel multi-standard signals. Finally, further improvements regarding two key limitations inherent to current all-digital transmitter approaches are then addressed, namely the poor coding efficiency and the combined high quality factor and tunability requirements of the RF output filter. The followed design approach based on poliphase multipath circuits allowed to create a new FPGA-embedded agile transmitter architecture that significantly improves important figures of merit, such as coding efficiency and SNR, while maintains the high flexibility that is required for supporting multichannel multimode data transmission.Transmissores de rádio flexíveis baseados no conceito do Rádio Definido por Software (SDR) estão a receber uma crescente importância de investigação essencialmente devido à proliferação sem precedentes de novos standards de comunicações wireless que trabalham em frequências diferentes, usando esquemas de modulação e codificação dissimilares, estando direcionados para os mais diversos fins. Neste novo paradigma de comunicações wireless, a camada física do transmissor rádio tem de ser capaz de suportar a transmissão simultânea de sinais provenientes de diferentes standards, operando em diferentes bandas de frequências e com diferentes ritmos de transmissão, o que na prática é muito difícil ou muito ineficiente de implementar utilizando abordagens convencionais. Contudo, os últimos desenvolvimentos nesta área incluem novas arquiteturas de transmissão inteiramente digitais onde o datapath do rádio é digital desde a banda base até ao RF. Tal conceito tem uma elevada flexibilidade e representa um passo importante para o desenvolvimento de transmissores baseados em SDR. No entanto, a implementação de tal rádio para cenários de comunicação reais é uma tarefa desafiadora, onde algumas limitações chave estão ainda impedindo uma maior adopção deste conceito. Esta tese tem como principal objetivo o de investigar algumas destas limitações, propondo e implementando arquiteturas inovadoras de transmissão inteiramente digitais com inerente elevada flexibilidade e integração, e onde melhorar importantes figuras de mérito, tais como a eficiência de codificação, a relação sinal-ruído, a largura de banda utilizável e o ruído dentro e fora da banda também serão abordadas. Na primeira parte deste trabalho é introduzido o conceito de transmissão de dados RF utilizando uma abordagem totalmente digital, baseada em modulação por impulsos. Uma comparação entre diversas tecnologias de implementação é também apresentada, permitindo afirmar que as FPGAs actuais oferecem um compromisso interessante entre desempenho, eficiência de energia e flexibilidade, tornando-as uma escolha interessante como uma tecnologia de implementação com elevado potencial para transmissores completamente digitais baseados em moduladores pulsados. Após esta discussão são apresentados os conceitos fundamentais inerentes aos moduladores pulsados e introduzidos os avanços relativos a transmissores RF modulados por pulsos, juntamente com vários exemplos de arquiteturas do estado da arte encontrados na literatura. Em seguida, o núcleo desta tese contendo os principais desenvolvimentos alcançados durante este trabalho de doutoramento é apresentado e discutido. O primeiro contributo fundamental para o estado da arte aqui apresentado consiste no desenvolvimento e integração em FPGA de uma nova arquitetura de transmissão inteiramente digital, baseada em moduladores ΣΔ e dotada de uma elevada flexibilidade e integração, sendo capaz de transmitir dados de multiplos standards e em multiplas bandas de RF. Uma segunda contribuição chave relativa à transmissão simultânea de vários sinais RF é então introduzida, sendo apresentadas e descritas novas arquiteturas de transmissão de sinal RF inteiramente digitais, as quais tiram proveito de serializadores de dados multi-gigabit disponíveis em FPGAs atuais de alto desempenho. Melhorias adicionais a esta abordagem permitiram desenvolver uma arquitetura de transmissão com duas fases de conversão na frequência, a qual permite a transmissão concorrente de sinais multistandard e multicanal com ajuste fino na frequência. Por ultimo, foram ainda investigadas diversas técnicas que visam reduzir duas limitações fundamentais inerentes aos actuais transmissores completamente digitais, nomeadamente, a baixa eficiência de codificação dos moduladores pulsados e o elevado fator de qualidade combinado com elevados requisitos de adaptabilidade na frequencia do filtro de reconstrução do sinal RF a transmitir. A abordagem seguida baseada em multiplos caminhos polifásicos permitiu desenvolver uma nova arquitetura de transmissão integrada em FPGA que melhora de forma significativa importantes figuras de mérito, tais como a eficiência de codificação e SNR, enquanto mantém a elevada flexibilidade que é necessária para suportar a transmissão de dados multimodo e multicanal

    Doctor of Philosophy

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    dissertationWireless communications pervade all avenues of modern life. The rapid expansion of wireless services has increased the need for transmission schemes that are more spectrally efficient. Dynamic spectrum access (DSA) systems attempt to address this need by building a network where the spectrum is used opportunistically by all users based on local and regional measurements of its availability. One of the principal requirements in DSA systems is to initialize and maintain a control channel to link the nodes together. This should be done even before a complete spectral usage map is available. Additionally, with more users accessing the spectrum, it is important to maintain a stable link in the presence of significant interference in emergency first-responders, rescue, and defense applications. In this thesis, a new multicarrier spread spectrum (MC-SS) technique based on filter banks is presented. The new technique is called filter bank multicarrier spread spectrum (FB-MC-SS). A detailed theory of the underlying properties of this signal are given, with emphasis on the properties that lend themselves to synchronization at the receiver. Proposed algorithms for synchronization, channel estimation, and detection are implemented on a software-defined radio platform to complete an FB-MC-SS transceiver and to prove the practicality of the technique. FB-MC-SS is shown through physical experimentation to be significantly more robust to partial band interference compared to direct sequence spread spectrum. With a higher power interfering signal occupying 90% of its band, FB-MC-SS maintains a low bit error rate. Under the same interference conditions, DS-SS fails completely. This experimentation leads to a theoretical analysis that shows in a frequency selective channel with additive white noise, the FB-MC-SS system has performance that equals that obtained by a DS-SS system employing an optimal rake receiver. This thesis contains a detailed chapter on implementation and design, including lessons learned while prototyping the system. This is to assist future system designers to quickly gain proficiency in further development of this technology

    Integrated radio frequency synthetizers for wireless applications

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    This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

    High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

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    The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

    Performance enhancement for LTE and beyond systems

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    A thesis submitted to the University of Bedfordshire, in partial fulfilment of the requirements for the degree of Doctor of PhilosophyWireless communication systems have undergone fast development in recent years. Based on GSM/EDGE and UMTS/HSPA, the 3rd Generation Partnership Project (3GPP) specified the Long Term Evolution (LTE) standard to cope with rapidly increasing demands, including capacity, coverage, and data rate. To achieve this goal, several key techniques have been adopted by LTE, such as Multiple-Input and Multiple-Output (MIMO), Orthogonal Frequency-Division Multiplexing (OFDM), and heterogeneous network (HetNet). However, there are some inherent drawbacks regarding these techniques. Direct conversion architecture is adopted to provide a simple, low cost transmitter solution. The problem of I/Q imbalance arises due to the imperfection of circuit components; the orthogonality of OFDM is vulnerable to carrier frequency offset (CFO) and sampling frequency offset (SFO). The doubly selective channel can also severely deteriorate the receiver performance. In addition, the deployment of Heterogeneous Network (HetNet), which permits the co-existence of macro and pico cells, incurs inter-cell interference for cell edge users. The impact of these factors then results in significant degradation in relation to system performance. This dissertation aims to investigate the key techniques which can be used to mitigate the above problems. First, I/Q imbalance for the wideband transmitter is studied and a self-IQ-demodulation based compensation scheme for frequencydependent (FD) I/Q imbalance is proposed. This combats the FD I/Q imbalance by using the internal diode of the transmitter and a specially designed test signal without any external calibration instruments or internal low-IF feedback path. The instrument test results show that the proposed scheme can enhance signal quality by 10 dB in terms of image rejection ratio (IRR). In addition to the I/Q imbalance, the system suffers from CFO, SFO and frequency-time selective channel. To mitigate this, a hybrid optimum OFDM receiver with decision feedback equalizer (DFE) to cope with the CFO, SFO and doubly selective channel. The algorithm firstly estimates the CFO and channel frequency response (CFR) in the coarse estimation, with the help of hybrid classical timing and frequency synchronization algorithms. Afterwards, a pilot-aided polynomial interpolation channel estimation, combined with a low complexity DFE scheme, based on minimum mean squared error (MMSE) criteria, is developed to alleviate the impact of the residual SFO, CFO, and Doppler effect. A subspace-based signal-to-noise ratio (SNR) estimation algorithm is proposed to estimate the SNR in the doubly selective channel. This provides prior knowledge for MMSE-DFE and automatic modulation and coding (AMC). Simulation results show that this proposed estimation algorithm significantly improves the system performance. In order to speed up algorithm verification process, an FPGA based co-simulation is developed. Inter-cell interference caused by the co-existence of macro and pico cells has a big impact on system performance. Although an almost blank subframe (ABS) is proposed to mitigate this problem, the residual control signal in the ABS still inevitably causes interference. Hence, a cell-specific reference signal (CRS) interference cancellation algorithm, utilizing the information in the ABS, is proposed. First, the timing and carrier frequency offset of the interference signal is compensated by utilizing the cross-correlation properties of the synchronization signal. Afterwards, the reference signal is generated locally and channel response is estimated by making use of channel statistics. Then, the interference signal is reconstructed based on the previous estimate of the channel, timing and carrier frequency offset. The interference is mitigated by subtracting the estimation of the interference signal and LLR puncturing. The block error rate (BLER) performance of the signal is notably improved by this algorithm, according to the simulation results of different channel scenarios. The proposed techniques provide low cost, low complexity solutions for LTE and beyond systems. The simulation and measurements show good overall system performance can be achieved
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