A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Carbon Nanotube Interconnect Modeling for Very Large Scale Integrated Circuits

In this research, we have studied and analyzed the physical and electrical properties of carbon nanotubes. Based on the reported models for current transport behavior in non-ballistic CNT-FETs, we have built a dynamic model for non-ballistic CNT-FETs. We have also extended the surface potential model of a non-ballistic CNT-FET to a ballistic CNT-FET and developed a current transport model for ballistic CNT-FETs. We have studied the current transport in metallic carbon nanotubes. By considering the electron-electron interactions, we have modified two-dimensional fluid model for electron transport to build a semi-classical one-dimensional fluid model to describe the electron transport in carbon nanotubes, which is regarded as one-dimensional system. Besides its accuracy compared with two-dimensional fluid model and Lüttinger liquid theory, one-dimensional fluid model is simple in mathematical modeling and easier to extend for electronic transport modeling of multi-walled carbon nanotubes and single-walled carbon nanotube bundles as interconnections. Based on our reported one-dimensional fluid model, we have calculated the parameters of the transmission line model for the interconnection wires made of single-walled carbon nanotube, multi-walled carbon nanotube and single-walled carbon nanotube bundle. The parameters calculated from these models show close agreements with experiments and other proposed models. We have also implemented these models to study carbon nanotube for on-chip wire inductors and it application in design of LC voltage-controlled oscillators. By using these CNT-FET models and CNT interconnects models, we have studied the behavior of CNT based integrated circuits, such as the inverter, ring oscillator, energy recovery logic; and faults in CNT based circuits

Efficient Transfer Doping of Carbon Nanotube Forests by MoO3.

We dope nanotube forests using evaporated MoO3 and observe the forest resistivity to decrease by 2 orders of magnitude, reaching values as low as ∼5 × 10(-5) Ωcm, thus approaching that of copper. Using in situ photoemission spectroscopy, we determine the minimum necessary MoO3 thickness to dope a forest and study the underlying doping mechanism. Homogenous coating and tube compaction emerge as key factors for decreasing the forest resistivity. When all nanotubes are fully coated with MoO3 and packed, conduction channels are created both inside the nanotubes and on the outside oxide layer. This is supported by density functional theory calculations, which show a shift of the Fermi energy of the nanotubes and the conversion of the oxide into a layer of metallic character. MoO3 doping removes the need for chirality control during nanotube growth and represents a step forward toward the use of forests in next-generation electronics and in power cables or conductive polymers.The authors acknowledge financial support from European project Grafol.This is the accepted manuscript. The final version is available at http://pubs.acs.org/doi/full/10.1021/acsnano.5b04644

Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles

Fundamental Characterization of Low Dimensional Carbon Nanomaterials for 3D Electronics Packaging

Transistor miniaturization has over the last half century paved the way for higher value electronics every year along an exponential pace known as \u27Moore\u27s law\u27. Now, as the industry is reaching transistor features that no longer makes economic sense, this way of developing integrated circuits (ICs) is coming to its definitive end. As a solution to this problem, the industry is moving toward higher hanging fruits that can enable larger sets of functionalities and ensuring a sustained performance increase to continue delivering more cost-effective ICs every product cycle. These design strategies beyond Moore\u27s law put emphasis on 3D stacking and heterogeneous integration, which if implemented correctly, will deliver a continued development of ICs for a foreseeable future. However, this way of building semiconductor systems does bring new issues to the table as this generation of devices will place additional demands on materials to be successful. The international roadmap of devices and systems (IRDS) highlights the need for improved materials to remove bottlenecks in contemporary as well as future systems in terms of thermal dissipation and interconnect performance. For this very purpose, low dimensional carbon nanomaterials such as graphene and carbon nanotubes (CNTs) are suggested as potential candidates due to their superior thermal, electrical and mechanical properties. Therefore, a successful implementation of these materials will ensure a continued performance to cost development of IC devices.This thesis presents a research study on some fundamental materials growth and reliability aspects of low dimensional carbon based thermal interface materials (TIMs) and interconnects for electronics packaging applications. Novel TIMs and interconnects based on CNT arrays and graphene are fabricated and investigated for their thermal resistance contributions as well electrical performance. The materials are studied and optimized with the support of chemical and structural characterization. Furthermore, a reliability study was performed which found delamination issues in CNT array TIMs due to high strains from thermal expansion mismatches. This study concludes that CNT length is an important factor when designing CNT based systems and the results show that by further interface engineering, reliability can be substantially improved with maintained thermal dissipation and electrical performance. Additionally, a heat treatment study was made that enables improvement of the bulk crystallinity of the materials which will enable even better performance in future applications

Single-step CVD growth of high-density carbon nanotube forests on metallic Ti coatings through catalyst engineering

We demonstrate the direct growth of carbon nanotube (CNT) forests on metallic titanium (Ti) coatings by single-step chemical vapor deposition. This was achieved by catalyst engineering, which involves a novel design of Fe/Ti/Fe nanostructure sputtering coated on SiO2/Si wafers. The Fe sublayer, an additional catalyst added to the conventional catalyst/support design, plays a key role in the growth of well aligned and highly dense CNT forests. Depth profile analysis of substrates by secondary ion mass spectroscopy shows that the Fe sublayer is thermally unstable at the Ti/SiO2 interface under the growth conditions. Catalyst diffusion back to the surface from the Fe sublayer is much more significant than down towards the SiO2/Si substrate from the surface Fe layer. This makes it possible to minimize the thickness of surface catalyst layer, and ensures the growth of well aligned and high-density CNT forests on Ti coatings. The filling factor of nanotubes on the substrate after liquid-induced compaction can be dramatically increased up to 57%, leading to an estimation of the areal density of around 1012 cm−2.The authors are grateful to the EC funding of Viacarbon and Technotubes projects.This is the author accepted manuscript. The final version can be found on the publisher's website at: http://www.sciencedirect.com/science/article/pii/S0008622313010191 © 2013 Elsevier Ltd. All rights reserved

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc