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Survey of partitioning techniques in silicon compilation
In the silicon compilation design process, partitioning is usually the first problem to be investigated because partitioning algorithms form the backbone of many algorithms including: system synthesis, processor synthesis, floorplanning, and placement. In this survey, several partitioning techniques will be examined. In addition, this paper will review the partitioning algorithms used by synthesis systems at different design levels
Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures
Quantum computers have recently made great strides and are on a long-term
path towards useful fault-tolerant computation. A dominant overhead in
fault-tolerant quantum computation is the production of high-fidelity encoded
qubits, called magic states, which enable reliable error-corrected computation.
We present the first detailed designs of hardware functional units that
implement space-time optimized magic-state factories for surface code
error-corrected machines. Interactions among distant qubits require surface
code braids (physical pathways on chip) which must be routed. Magic-state
factories are circuits comprised of a complex set of braids that is more
difficult to route than quantum circuits considered in previous work [1]. This
paper explores the impact of scheduling techniques, such as gate reordering and
qubit renaming, and we propose two novel mapping techniques: braid repulsion
and dipole moment braid rotation. We combine these techniques with graph
partitioning and community detection algorithms, and further introduce a
stitching algorithm for mapping subgraphs onto a physical machine. Our results
show a factor of 5.64 reduction in space-time volume compared to the best-known
previous designs for magic-state factories.Comment: 13 pages, 10 figure
Floorplan-guided placement for large-scale mixed-size designs
In the nanometer scale era, placement has become an extremely challenging stage in modern Very-Large-Scale Integration (VLSI) designs. Millions of objects need to be placed legally within a chip region, while both the interconnection and object distribution have to be optimized simultaneously. Due to the extensive use of Intellectual Property (IP) and embedded memory blocks, a design usually contains tens or even hundreds of big macros. A design with big movable macros and numerous standard cells is known as mixed-size design. Due to the big size difference between big macros and standard cells, the placement of mixed-size designs is much more difficult than the standard-cell placement.
This work presents an efficient and high-quality placement tool to handle modern large-scale mixed-size designs. This tool is developed based on a new placement algorithm flow. The main idea is to use the fixed-outline floorplanning algorithm to guide the state-of-the-art analytical placer. This new flow consists of four steps: 1) The objects in the original netlist are clustered into blocks; 2) Floorplanning is performed on the blocks; 3) The blocks are shifted within the chip region to further optimize the wirelength; 4) With big macro locations fixed, incremental placement is applied to place the remaining objects. Several key techniques are proposed to be used in the first two steps. These techniques are mainly focused on the following two aspects: 1) Hypergraph clustering algorithm that can cut down the original problem size without loss of placement Quality of Results (QoR); 2) Fixed-outline floorplanning algorithm that can provide a good guidance to the analytical placer at the global level.
The effectiveness of each key technique is demonstrated by promising experimental results compared with the state-of-the-art algorithms. Moreover, using the industrial mixed-size designs, the new placement tool shows better performance than other existing approaches
The IPS fidelity scale as a guideline to implement Supported Employment
info:eu-repo/semantics/publishe
Community Detection via Maximization of Modularity and Its Variants
In this paper, we first discuss the definition of modularity (Q) used as a
metric for community quality and then we review the modularity maximization
approaches which were used for community detection in the last decade. Then, we
discuss two opposite yet coexisting problems of modularity optimization: in
some cases, it tends to favor small communities over large ones while in
others, large communities over small ones (so called the resolution limit
problem). Next, we overview several community quality metrics proposed to solve
the resolution limit problem and discuss Modularity Density (Qds) which
simultaneously avoids the two problems of modularity. Finally, we introduce two
novel fine-tuned community detection algorithms that iteratively attempt to
improve the community quality measurements by splitting and merging the given
network community structure. The first of them, referred to as Fine-tuned Q, is
based on modularity (Q) while the second one is based on Modularity Density
(Qds) and denoted as Fine-tuned Qds. Then, we compare the greedy algorithm of
modularity maximization (denoted as Greedy Q), Fine-tuned Q, and Fine-tuned Qds
on four real networks, and also on the classical clique network and the LFR
benchmark networks, each of which is instantiated by a wide range of
parameters. The results indicate that Fine-tuned Qds is the most effective
among the three algorithms discussed. Moreover, we show that Fine-tuned Qds can
be applied to the communities detected by other algorithms to significantly
improve their results
Access and metro network convergence for flexible end-to-end network design
This paper reports on the architectural, protocol, physical layer, and integrated testbed demonstrations carried out by the DISCUS FP7 consortium in the area of access - metro network convergence. Our architecture modeling results show the vast potential for cost and power savings that node consolidation can bring. The architecture, however, also recognizes the limits of long-reach transmission for low-latency 5G services and proposes ways to address such shortcomings in future projects. The testbed results, which have been conducted end-to-end, across access - metro and core, and have targeted all the layers of the network from the application down to the physical layer, show the practical feasibility of the concepts proposed in the project
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