Improving EHW performance introducing a new decomposition strategy

This paper describes a new type of decomposition strategy for Evolvable Hardware, which tackles the problem of scalability. Several logic circuits from the MCNC benchmark have been evolved and compared with other Evolvable Hardware techniques. The results demonstrate that the proposed method improves the evolution of logic circuits in terms of time and fitness function in comparison with BIE and standard EHW

Double Helix Structure and Finite Persisting Sphere Genetic Algorithm in Designing Digital Circuit Structure

This paper proposes a new approach of chromosome representation in digital circuit design which is Double Helix Structure (DHS). The idea of DHS in chromosome representation is inspired from the nature of the DNA\u27s structure that built up the formation of the chromosomes. DHS is an uncomplicated design method. It uses short chromosome string to represent the circuit structure. This new structure representation is flexible in size where it is not restricted by the conventional matrix structure representation. There are some advantages of the proposed method such as convenience to apply due to the simple formation and flexible structure, less requirement of memory allocation and faster processing time due to the short chromosomes representation. In this paper, DHS is combined with Finite Persisting Sphere Genetic Algorithm (FPSGA) to optimal the digital circuit structure design. The experimental results prove that DHS uses short chromosome string to produce the flexible digital circuit structure and FPSGA further optimal the number of gates used in the structure. The proposed method has better performance compared to other methods

Digital Circuit Design Through Simulated Evolution (SimE)

Abstract- In this paper, the use of Simulated Evolution (SimE) Algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection and allocation. Two goodness measures are designed to guide the selection and allocation operations of SimE. Area, power and delay are considered in the optimization of circuits. Results obtained by SimE algorithm are compared to those obtained by Genetic Algorithm (CA)

Tiny Classifier Circuits: Evolving Accelerators for Tabular Data

A typical machine learning (ML) development cycle for edge computing is to maximise the performance during model training and then minimise the memory/area footprint of the trained model for deployment on edge devices targeting CPUs, GPUs, microcontrollers, or custom hardware accelerators. This paper proposes a methodology for automatically generating predictor circuits for classification of tabular data with comparable prediction performance to conventional ML techniques while using substantially fewer hardware resources and power. The proposed methodology uses an evolutionary algorithm to search over the space of logic gates and automatically generates a classifier circuit with maximised training prediction accuracy. Classifier circuits are so tiny (i.e., consisting of no more than 300 logic gates) that they are called "Tiny Classifier" circuits, and can efficiently be implemented in ASIC or on an FPGA. We empirically evaluate the automatic Tiny Classifier circuit generation methodology or "Auto Tiny Classifiers" on a wide range of tabular datasets, and compare it against conventional ML techniques such as Amazon's AutoGluon, Google's TabNet and a neural search over Multi-Layer Perceptrons. Despite Tiny Classifiers being constrained to a few hundred logic gates, we observe no statistically significant difference in prediction performance in comparison to the best-performing ML baseline. When synthesised as a Silicon chip, Tiny Classifiers use 8-18x less area and 4-8x less power. When implemented as an ultra-low cost chip on a flexible substrate (i.e., FlexIC), they occupy 10-75x less area and consume 13-75x less power compared to the most hardware-efficient ML baseline. On an FPGA, Tiny Classifiers consume 3-11x fewer resources.Comment: 14 pages, 16 figure

A Hierarchical Approach to Computer-Aided Design of Quantum Circuits

A new approach to synthesis of permutation class of quantum logic circuits has been proposed in this paper. This approach produces better results than the previous approaches based on classical reversible logic and can be easier tuned to any particular quantum technology such as nuclear magnetic resonance (NMR). First we synthesize a library of permutation (pseudobinary) gates using a Computer-Aided-Design approach that links evolutionary and combinatorics approaches with human experience and creativity. Next the circuit is designed using these gates and standard 1*1 and 2*2 quantum gates and finally the optimizing tautological transforms are applied to the circuit, producing a sequence of quantum operations being close to operations practically realizable. These hierarchical stages can be compared to standard gate library design, generic logic synthesis and technology mapping stages of classical CAD systems, respectively. We use an informed genetic algorithm to evolve arbitrary quantum circuit specified by a (target) unitary matrix, specific encoding that reduces the time of calculating the resultant unitary matrices of chromosomes, and an evolutionary algorithm specialized to permutation circuits specified by truth tables. We outline interactive CAD approach in which the designer is a part of feedback loop in evolutionary program and the search is not for circuits of known specifications, but for any gates with high processing power and small cost for given constraints. In contrast to previous approaches, our methodology allows synthesis of both: small quantum circuits of arbitrary type (gates), and permutation class circuits that are well realizable in particular technology