Nanoscale resistive switching memory devices: a review

In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I–V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Hardware/Software Co-Design of Ultra-Low Power Biomedical Monitors

Ongoing changes in world demographics and the prevalence of unhealthy lifestyles are imposing a paradigm shift in healthcare delivery. Nowadays, chronic ailments such as cardiovascular diseases, hypertension and diabetes, represent the most common causes of death according to the World Health Organization. It is estimated that 63% of deaths worldwide are directly or indirectly related to these non-communicable diseases (NCDs), and by 2030 it is predicted that the health delivery cost will reach an amount comparable to 75% of the current GDP. In this context, technologies based on Wireless Sensor Nodes (WSNs) effectively alleviate this burden enabling the conception of wearable biomedical monitors composed of one or several devices connected through a Wireless Body Sensor Network (WBSN). Energy efficiency is of paramount importance for these devices, which must operate for prolonged periods of time with a single battery charge. In this thesis I propose a set of hardware/software co-design techniques to drastically increase the energy efficiency of bio-medical monitors. To this end, I jointly explore different alternatives to reduce the required computational effort at the software level while optimizing the power consumption of the processing hardware by employing ultra-low power multi-core architectures that exploit DSP application characteristics. First, at the sensor level, I study the utilization of a heartbeat classifier to perform selective advanced DSP on state-of-the-art ECG bio-medical monitors. To this end, I developed a framework to design and train real-time, lightweight heartbeat neuro-fuzzy classifiers, detail- ing the required optimizations to efficiently execute them on a resource-constrained platform. Then, at the network level I propose a more complex transmission-aware WBSN for activity monitoring that provides different tradeoffs between classification accuracy and transmission volume. In this work, I study the combination of a minimal set of WSNs with a smartphone, and propose two classification schemes that trade accuracy for transmission volume. The proposed method can achieve accuracies ranging from 88% to 97% and can save up to 86% of wireless transmissions, outperforming the state-of-the-art alternatives. Second, I propose a synchronization-based low-power multi-core architecture for bio-signal processing. I introduce a hardware/software synchronization mechanism that allows to achieve high energy efficiency while parallelizing the execution of multi-channel DSP applications. Then, I generalize the methodology to support bio-signal processing applications with an arbitrarily high degree of parallelism. Due to the benefits of SIMD execution and software pipelining, the architecture can reduce its power consumption by up 38% when compared to an equivalent low-power single-core alternative. Finally, I focused on the optimization of the multi-core memory subsystem, which is the major contributor to the overall system power consumption. First I considered a hybrid memory subsystem featuring a small reliable partition that can operate at ultra-low voltage enabling low-power buffering of data and obtaining up to 50% energy savings. Second, I explore a two-level memory hierarchy based on non-volatile memories (NVM) that allows for aggressive fine-grained power gating enabled by emerging low-power NVM technologies and monolithic 3D integration. Experimental results show that, by adopting this memory hierarchy, power consumption can be reduced by 5.42x in the DSP stage

Advance in Energy Harvesters/Nanogenerators and Self-Powered Sensors

This reprint is a collection of the Special Issue "Advance in Energy Harvesters/Nanogenerators and Self-Powered Sensors" published in Nanomaterials, which includes one editorial, six novel research articles and four review articles, showcasing the very recent advances in energy-harvesting and self-powered sensing technologies. With its broad coverage of innovations in transducing/sensing mechanisms, material and structural designs, system integration and applications, as well as the timely reviews of the progress in energy harvesting and self-powered sensing technologies, this reprint could give readers an excellent overview of the challenges, opportunities, advancements and development trends of this rapidly evolving field

Etude des cellules mémoires résistives RRAM à base de HfO2 par caractérisation électrique et simulations atomistiques

Among non-volatile memory technologies, NAND Flash represents a significant portion in the IC market and has benefitted from the traditional scaling of semiconductor industry allowing its high density integration. However, this scaling seems to be problematic beyond the 22 nm node. In an effort to go beyond this scaling limitation, alternative memory solutions are proposed among which Resistive RAM (RRAM) stands out as a serious candidate for NAND Flash replacement. Hence, in this PhD thesis we try to respond to many open questions about RRAM devices based on hafnium oxide (HfO2), in particular, by addressing the lack of detailed physical comprehension about their operation and reliability. The impact of scaling, the role of electrodes, the process of defects formation and diffusion are investigated. The impact of alloying/doping HfO2 with other materials for improved RRAM performance is also studied. Finally, our study attempts to provide some answers on the conductive filament formation, its stability and possible composition.La mémoire NAND Flash représente une part importante dans le marché des circuits intégrés et a bénéficié de la traditionnelle miniaturisation de l’industrie des sémiconducteurs lui permettant un niveau d’intégration élevé. Toutefois, cette miniaturisation semble poser des sérieux problèmes au-delà du noeud 22 nm. Dans un souci de dépasser cette limite, des solutions mémoires alternatives sont proposées parmi lesquelles la mémoire résistive (RRAM) se pose comme un sérieux candidat pour le remplacement de NAND Flash. Ainsi, dans cette thèse nous essayons de répondre à des nombreuses questions ouvertes sur les dispositifs RRAM à base d’oxyde d’hafnium (HfO2) en particulier en adressant le manque de compréhension physique détaillée sur leur fonctionnement et leur fiabilité. L’impact de la réduction de taille des RRAM, le rôle des électrodes et le processus de formation et de diffusion des défauts sont étudiés. L’impact de l’alliage/dopage de HfO2 avec d’autres matériaux pour l’optimisation des RRAM est aussi abordé. Enfin, notre étude tente de donner quelques réponses sur la formation du filament conducteur, sa stabilité et sa possible composition

Estudio de nuevas tecnologías para memorias no volátiles emergentes

[ES] Las tecnologías de memoria que constituyen el mercado actual están llegando a su límite de escalabilidad, y pronto la ley de Moore ya no podría aplicarse a estas tecnologías en su estado actual. La creciente demanda de más capacidad en el mismo espacio en Smartphones, cámaras digitales, reproductores de música, ordenadores, etc. y la ampliación del mercado de la memoria a la automoción y a la ropa inteligente, entre otras, hace más evidente la necesidad de avances en el campo del almacenamiento de datos. Diversas tecnologías desarrolladas a lo largo de las últimas décadas prometen combinar la velocidad de la SRAM, la densidad de almacenamiento de la DRAM o superior, y la no volatilidad de los datos que presenta la tecnología Flash, a un precio no muy alto. Una memoria con estas características sería capaz de revolucionar el mercado, cambiando por completo la jerarquía de memoria tal y como la conocemos ahora, y provocando más repercusión que la memoria Flash en la última década. Este trabajo se centra en analizar las diversas tecnologías de memoria no volátil que han surgido en los últimos años, especialmente las que poseen productos en el mercado actual, así como realizar una comparación entre éstas y las tecnologías clásicas. Para ello se ha efectuado un exhaustivo estudio bibliográfico a partir de publicaciones punteras, que se ha complementado con un análisis mediante algunas plataformas de simulación relevantes .[EN] Abstract The memory technologies that make up the current market are reaching their limit of scalability, and soon Moore's law could no longer apply to these technologies in their current state. The growing demand for storing more data in the same space in Smartphones, digital cameras, music players, computers, etc. and the expansion of the memory market to the automotive industry and smart clothing, among others, makes the need for advances in the field of data storage more evident. Several technologies developed over the last few decades promise to combine the speed of the SRAM, the storage density of the DRAM or higher, and the non-volatility of the Flash technology, at less cost. A memory with these characteristics would be able to revolutionize the market, completely changing the memory hierarchy as we know it now, and causing more impact than Flash memory in the last decade. This work focuses on analyzing the various non-volatile memory technologies that have emerged in recent years, especially those that have products in the current market, as well as making a comparison between them and classical technologies. For this, an exhaustive bibliographic study has been carried out based on leading publications, which has been complemented with an analysis by means of some relevant simulation platforms.[CA] Les tecnologies de memòria que constituïxen el mercat actual estan arribant al seu límit d'escalabilitat, i prompte la llei de Moore ja no podria aplicar-se a estes tecnologies en el seu estat actual. La creixent demanda de més capacitat en el mateix espai en Smartphones, càmeres digitals, reproductors de música, ordinadors, etc. i l'ampliació del mercat de la memòria a l'automoció i a la roba intel·ligent, entre altres, fa més evident la necessitat d'avanços en el camp de l'emmagatzemament de dades. Diverses tecnologies desenrotllades al llarg de les últimes dècades prometen combinar la velocitat de la SRAM, la densitat d'emmagatzemament de la DRAM o superior, i la no volatilitat de les dades que presenta la tecnologia Flash, a un preu inferior. Una memòria amb estes característiques seria capaç de revolucionar el mercat, canviant per complet la jerarquia de memòria tal com la coneixem ara, i provocant més repercussió que la memòria Flash en l'última dècada. Este treball se centra a analitzar les diverses tecnologies de memòria no volàtil que han sorgit en els últims anys, especialment les que posseïxen productes en el mercat actual, així com realitzar una comparació entre estes i les tecnologies clàssiques. Per a això s'ha efectuat un exhaustiu estudi bibliogràfic a partir de publicacions punteres, que s'ha complementat amb una anàlisi per mitjà d'algunes plataformes de simulació rellevants.Aspas Coronado, I. (2019). Estudio de nuevas tecnologías para memorias no volátiles emergentes. http://hdl.handle.net/10251/128777TFG

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

Thermal Aware Design Automation of the Electronic Control System for Autonomous Vehicles

The autonomous vehicle (AV) technology, due to its tremendous social and economical benefits, is transforming the entire world in the coming decades. However, significant technical challenges still need to be overcome until AVs can be safely, reliably, and massively deployed. Temperature plays a key role in the safety and reliability of an AV, not only because a vehicle is subjected to extreme operating temperatures but also because the increasing computations demand more powerful IC chips, which can lead to higher operating temperature and large thermal gradient. In particular, as the underpinning technology for AV, artificial intelligence (AI) requires substantially increased computation and memory resources, which have been growing exponentially through recent years and further exacerbated the thermal problems. High operating temperature and large thermal gradient can reduce the performance, degrade the reliability, and even cause an IC to fail catastrophically. We believe that dealing with thermal issues must be coupled closely in the design phase of the AVs’ electronic control system (ECS). To this end, first, we study how to map vehicle applications to ECS with heterogeneous architecture to satisfy peak temperature constraints and optimize latency and system-level reliability. We present a mathematical programming model to bound the peak temperature for the ECS. We also develop an approach based on the genetic algorithm to bound the peak temperature under varying execution time scenarios and optimize the system-level reliability of the ECS. We present several computationally efficient techniques for system-level mean-time-to-failure (MTTF) computation, which show several orders-of-magnitude speed-up over the state-of-the-art method. Second, we focus on studying the thermal impacts of AI techniques. Specifically, we study how the thermal impacts for the memory bit flipping can affect the prediction accuracy of a deep neural network (DNN). We develop a neuron-level analytical sensitivity estimation framework to quantify this impact and study its effectiveness with popular DNN architectures. Third, we study the problem of incorporating thermal impacts into mapping the parameters for DNN neurons to memory banks to improve prediction accuracy. Based on our developed sensitivity metric, we develop a bin-packing-based approach to map DNN neuron parameters to memory banks with different temperature profiles. We also study the problem of identifying the optimal temperature profiles for memory systems that can minimize the thermal impacts. We show that the thermal aware mapping of DNN neuron parameters on memory banks can significantly improve the prediction accuracy at a high-temperature range than the thermal ignorant for state-of-the-art DNNs