Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Advanced III-V / Si nano-scale transistors and contacts: Modeling and analysis

The exponential miniaturization of Si CMOS technology has been a key to the electronics revolution. However, the continuous downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Hence, novel devices and better channel materials than Si are considered to improve the metal-oxide-semiconductor field-effect transistors (MOSFETs) device performance. III-V compound semiconductors and multi-gate structures are being considered as promising candidates in the next CMOS technology. III-V and Si nano-scale transistors in different architectures are investigated (1) to compare the performance between InGaAs of III-V compound semiconductors and strained-Si in planar FETs and triple-gate non-planar FinFETs. (2) to demonstrate whether or not these technologies are viable alternatives to Si and conventional planar FETs. The simulation results indicate that III-V FETs do not outperform Si FETs in the ballistic transport regime, and triple-gate FinFETs surely represent the best architecture for sub-15nm gate contacts, independently from the choice of channel material. ^ This work also proves that the contact resistance becomes a limiting factor of device performance as it takes larger fraction of the total on-state resistance. Hence, contact resistance must be reduced to meet the next ITRS requirements. However, from a modeling point of view, the understanding of the contacts still remains limited due to its size and multiple associated scattering effects, while the intrinsic device performance can be projected. Therefore, a precise theoretical modeling is required to advance optimized contact design to improve overall device performance. In this work, various factors of the contact resistances are investigated within realistic contact-to-channel structure of III-V quantum well field-effect transistors (QWFET). The key finding is that the contact-to-channel resistance is mainly caused by structural reasons: 1) barriers between multiple layers in the contact region 2) Schottky barrier between metal and contact pad. These two barriers work as bottleneck of the system conductance. The extracted contact resistance matches with the experimental value. The approximation of contact resistance from quantum transport simulation can be very useful to guide better contact designs of the future technology nodes. ^ The theoretical modeling of these nano-scale devices demands a proper treatment of quantum effects such as the energy-level quantization caused by strong quantum confinement of electrons and band structure non-parabolicity. 2-D and 3-D quantum transport simulator that solves non-equilibrium Green\u27s functions (NEGF) transport and Poisson equations self-consistently within a real-space effective mass approximation. The sp3d5s* empirical tight-binding method is employed to include non-parabolicity to obtain more accurate effective masses in confined nano-structures. The accomplishment of this work would aid in designing, engineering and manufacturing nano-scale devices, as well as next-generation microchips and other electronics with nano-scale features

Dielectric-Modulated TFETs as Label-Free Biosensors

This chapter presents tunnel field effect transistors (TFETs) as dielectric-modulated (DM) label-free biosensors, and discusses various aspects related to them. A brief survey of the dielectric-modulated TFET biosensors is presented. The concept of dielectric modulation in TFETs is discussed with focus on principle and design perspectives. A Technology Computer Aided Design (TCAD) based approach to incorporate embedded nanogaps in TFET geometries along with appropriate physics-based simulation models are mentioned. Non-ideal conditions in dielectric-modulated biosensors are brought to light, keeping in view the practical considerations of the devices. A gate engineered TFET is taken up for analysis of sensitivities under different conditions through TCAD simulations. Finally, a status map of the sensitivities of the most significant works in dielectric-modulated label-free biosensors is depicted, and the status of the proposed TFET is highlighted