A Robust Self-calibrating Transmission Scheme for On-Chip Networks

Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. We examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals

The fabrication and integration of pillar array channels for chip based separations and analysis

The fundamental motivations for scaling existing technological platforms down to lab on chip dimensions are applicable in nearly all scientific disciplines. These motivations include decreasing waste, improving throughput, and decreasing time consumption. Analytical tools, such as chromatographic separation devices, can additionally benefit from system miniaturization by utilizing wafer-level fabrication technology, allowing for the rational design and precise control of variables which ultimately affect separation performance. With the use of microfabrication techniques, we have developed an original processing sequence for the fabrication of silicon oxide enclosed pillar arrays integrated within a fluidic channel. These pillar arrays create a highly uniform submicron scale architecture of solid supports for subsequent stationary phase – mobile phase interactions, while demonstrating substantial improvements in separation efficiency and permeability over traditional packed bed and monolithic columns. The general performance of these microfluidic devices is studied by optimizing the chip architecture and instrumental design to improve the stability of the pillar arrays, improve the sample injection, enhance the pillar surface characteristics, and improve the separation performance. We additionally explore simple and straightforward stationary phase modification techniques for partition based chromatography. Finally, we address the detection challenges of our design by creating the first fully integrated microfluidic chip based platform to combine separation capabilities with real time surface enhanced Raman detection

R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging

This report reviews current trends in the R&D of semiconductor pixellated sensors for vertex tracking and radiation imaging. It identifies requirements of future HEP experiments at colliders, needed technological breakthroughs and highlights the relation to radiation detection and imaging applications in other fields of science.Comment: 17 pages, 2 figures, submitted to the European Strategy Preparatory Grou

Advances in High-Energy-Resolution CdZnTe Linear Array Pixel Detectors with Fast and Low Noise Readout Electronics

: Radiation detectors based on Cadmium Zinc Telluride (CZT) compounds are becoming popular solutions thanks to their high detection efficiency, room temperature operation, and to their reliability in compact detection systems for medical, astrophysical, or industrial applications. However, despite a huge effort to improve the technological process, CZT detectors' full potential has not been completely exploited when both high spatial and energy resolution are required by the application, especially at low energies (<10 keV), limiting their application in energy-resolved photon counting (ERPC) systems. This gap can also be attributed to the lack of dedicated front-end electronics which can bring out the best in terms of detector spectroscopic performances. In this work, we present the latest results achieved in terms of energy resolution using SIRIO, a fast low-noise charge sensitive amplifier, and a linear-array pixel detector, based on boron oxide encapsulated vertical Bridgman-grown B-VB CZT crystals. The detector features a 0.25-mm pitch, a 1-mm thickness and is operated at a -700-V bias voltage. An equivalent noise charge of 39.2 el. r.m.s. (corresponding to 412 eV FWHM) was measured on the test pulser at 32 ns peaking time, leading to a raw resolution of 1.3% (782 eV FWHM) on the 59 keV line at room temperature (+20 °C) using an uncollimated 241Am, largely improving the current state of the art for CZT-based detection systems at such short peaking times, and achieving an optimum resolution of 0.97% (576 eV FWHM) at 1 µs peaking time. The measured energy resolution at the 122 keV line and with 1 µs peaking time of a 57Co raw uncollimated spectrum is 0.96% (1.17 keV). These activities are in the framework of an Italian collaboration on the development of energy-resolved X-ray scanners for material recycling, medical applications, and non-destructive testing in the food industry

Advances in High-Energy-Resolution CdZnTe Linear Array Pixel Detectors with Fast and Low Noise Readout Electronics

Radiation detectors based on Cadmium Zinc Telluride (CZT) compounds are becoming popular solutions thanks to their high detection efficiency, room temperature operation, and to their reliability in compact detection systems for medical, astrophysical, or industrial applications. However, despite a huge effort to improve the technological process, CZT detectors’ full potential has not been completely exploited when both high spatial and energy resolution are required by the application, especially at low energies (<10 keV), limiting their application in energy-resolved photon counting (ERPC) systems. This gap can also be attributed to the lack of dedicated front-end electronics which can bring out the best in terms of detector spectroscopic performances. In this work, we present the latest results achieved in terms of energy resolution using SIRIO, a fast low-noise charge sensitive amplifier, and a linear-array pixel detector, based on boron oxide encapsulated vertical Bridgman-grown B-VB CZT crystals. The detector features a 0.25-mm pitch, a 1-mm thickness and is operated at a −700-V bias voltage. An equivalent noise charge of 39.2 el. r.m.s. (corresponding to 412 eV FWHM) was measured on the test pulser at 32 ns peaking time, leading to a raw resolution of 1.3% (782 eV FWHM) on the 59 keV line at room temperature (+20 °C) using an uncollimated 241Am, largely improving the current state of the art for CZT-based detection systems at such short peaking times, and achieving an optimum resolution of 0.97% (576 eV FWHM) at 1 µs peaking time. The measured energy resolution at the 122 keV line and with 1 µs peaking time of a 57Co raw uncollimated spectrum is 0.96% (1.17 keV). These activities are in the framework of an Italian collaboration on the development of energy-resolved X-ray scanners for material recycling, medical applications, and non-destructive testing in the food industry

The Intermediate Band Solar Cell: Progress Toward the Realization of an Attractive Concept

The intermediate band (IB) solar cell has been proposed to increase the current of solar cells while at the same time preserving the output voltage in order to produce an efficiency that ideally is above the limit established by Shockley and Queisser in 1961. The concept is described and the present realizations and acquired understanding are explained. Quantum dots are used to make the cells but the efficiencies that have been achieved so far are not yet satisfactory. Possible ways to overcome the issues involved are depicted. Alternatively, and against early predictions, IB alloys have been prepared and cells that undoubtedly display the IB behavior have been fabricated, although their efficiency is still low. Full development of this concept is not trivial but it is expected that once the development of IB solar cells is fully mastered, IB solar cells should be able to operate in tandem in concentrators with very high efficiencies or as thin cells at low cost with efficiencies above the present ones

CMOS Approach to Compressed-domain Image Acquisition

A hardware implementation of a real-time compressed-domain image acquisition system is demonstrated. The system performs front-end computational imaging, whereby the inner product between an image and an arbitrarily-specified mask is implemented in silicon. The acquisition system is based on an intelligent readout integrated circuit (iROIC) that is capable of providing independent bias voltages to individual detectors, which enables implementation of spatial multiplication with any prescribed mask through a bias-controlled response-modulation mechanism. The modulated pixels are summed up in the image grabber to generate the compressed samples, namely aperture-coded coefficients, of an image. A rigorous bias-selection algorithm is presented to the readout circuit, which exploits the bias-dependent nature of the imager’s responsivity. Proven functionality of the hardware in transform coding compressed image acquisition, silicon-level compressive sampling, in pixel nonuniformity correction and hardware-level implementation of region-based enhancement is demonstrated