1,876 research outputs found
Wide-band multipath A to D converter for Cognitive Radio applications
This article presents a digital-enhanced radio frequency receiver for fast wide-band spectrum sensing. It is based on charge sampling and hybrid filter bank techniques. The charge sampling method is employed to design analog bandpass filters. Using a hybrid filter bank for wide-band analog-to-digital conversion improves the speed and resolution of the conversion. We propose to use these techniques in combination of frequencydivision multiplexing with time-division multiplexing to design an integrated, completely software reconfigurable and reliable backend of radio frequency receiver for cognitive radio applications
Use of frequency response masking technique in designing A/D converter for SDR.
Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2005.Analog-to-digital converters (ADCs) are required in almost all signal processing and communication
systems. They are often the most critical components, since they tend to determine the overall system
performance. Hence, it is important to determine their performance limitations and develop improved
realizations. One of the most challenging tasks for realizing software defined radio (SDR) is to move ND
conversion as close to the antenna as possible, this implies that the ADC has to sample the incoming
signal with a very high sample rate (over 100 MSample/s) and with a very high resolution (14 -to -16 bits).
To design and implement AID converters with such high performance, it is necessary to investigate new
designing techniques.
The focus in this work is on a particular type of potentially high-performance (high-resolution and highspeed)
analog-to-digital conversion technique, utilizing filter banks, where two or more ADCs are used in
the converter array in parallel together with asymmetric filter banks. The hybrid filter bank analog-todigital
converter (HFB ADC) utilizes analog filters (analysis filters) to allocate a frequency band to each
ADC in a converter array and digital synthesis filters to reconstruct the digitized signal. The HFB
improves the speed and resolution of the conversion, in comparison to the standard time-interleaving
technique by attenuating the effect of gain and phase mismatches between the ADCs.
Many of the designs available in the literature are compromising between some metrics: design
complexity, order of the filter bank (computation time) and the sharpness of the frequency response rolloff
(the transition from the pass band to the stop band).
In this dissertation, five different classes of near perfect magnitude reconstruction (NPMR) continuoustime
hybrid filter banks (CT HFBs) are proposed. In each of the five cases, two filter banks are designed;
analysis filter bank and synthesis filter bank. Since the systems are hybrid, continuous time IlR filter are
used to implement the analysis filter bank and digital filters are used for the synthesis filter bank. To
optimize the system, we used a new technique, known in the literature as frequency response masking
(FRM), to design the synthesis filter bank. In this technique, the sharp roll-off characteristics can be
achieved while keeping the complexity of the filter within practical range, this is done by splitting the
filter into two filters in cascade; model filter with relaxed roll-off characteristics followed by a masking
filter.
One of the main factors controlling the overall complexity of the filter is the way of designing the model
filter and that of designing the masking filter.
The dissertation proposes three combinations: use of HR model filter and IlR masking filter, HR model
filter/FIR masking filter and FIR model filter/FIR masking filter. To show the advantages of our designs,
we considered the cases of designing the synthesis filter as one filter, either FIR or IlR. These two filters
are used as base for comparison with our proposed designs (the use of masking response filter). The results showed the following:
1. Asymmetric hybrid filter banks alone are not sufficient for filters with sharp frequency response
roll-off especially for HR/FIR class.
2. All classes that utilize FRM in their synthesis filter banks gave a good performance in general in
comparison to conventional classes, such as the reduction of the order of filters
3. HR/HR FRM gave better performance than HR/FIR FRM.
4. Comparing HR/HR FRM using FIR masking filters and HR/IIR FRM using IIR masking filters,
the latter gave better performance (the performance is generally measured in terms of reduced
filter order).
5. All classes that use the FRM approach have a very low complexity, in terms of reduced filter
order. Our target was to design a system with the following overall characteristics: pass band
ripple of -0.01 dB, stop band minimum attenuation of - 40 dB and of response roll-off of 0.002.
Our calculations showed that the order of the conventional IIR/FIR filter that achieves such
characteristics is aboutN =2000. Using the FRM technique, the order N reduced to
aboutN = 244, N = 179 for IIRJFIR and IIR/IIR classes, respectively. This shows that the
technique is very effective in reducing the filter complexity.
6. The magnitude distortion and the aliasing noise are calculated for each design proposal and
compared with the theoretical values. The comparisons show that all our proposals result in
approximately perfect magnitude reconstruction (NPMR).
In conclusion, our proposal of using frequency-response masking technique to design the synthesis filter
bank can, to large extent, reduce the complexity of the system. The design of the system as a whole is
simplified by designing the synthesis filter bank separately from the design of the analysis filter bank. In
this case each bank is optimized separately. This implies that for SDR applications we are proposing the
use of the continuous-time HFB ADC (CT HFB ADC) structure utilizing FRM for digital filters
Design and Implementation of an RF Front-End for Software Defined Radios
Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro grammable signal processing devices, giving the radio the ability to change its op erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability.
Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system.
In this thesis, some of major building blocks of a Software defined radio are de signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block
of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii
Abstract
algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated
Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices
This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability.
For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality
Synthetic Aperture Radar (SAR) data processing
The available and optimal methods for generating SAR imagery for NASA applications were identified. The SAR image quality and data processing requirements associated with these applications were studied. Mathematical operations and algorithms required to process sensor data into SAR imagery were defined. The architecture of SAR image formation processors was discussed, and technology necessary to implement the SAR data processors used in both general purpose and dedicated imaging systems was addressed
Very Low-Noise Differential Radiometer at 30 GHz for the PLANCK LFI
The PLANCK mission of the European Space Agency is devoted to produce sky maps of the cosmic microwave background radiation. The low-frequency instrument is a wide-band cryogenic microwave radiometer array operating at 30, 44, and 70 GHz. The design, test techniques, and performance of the complete differential radiometer at 30 GHz are presented. This elegant breadboard 30-GHz radiometer is composed of a front-end module (FEM) assembled at the Jodrell Bank Observatory, Cheshire, U.K., and a back-end module assembled at the Universidad de Cantabria, Cantabria, Spain, and Telecomunicacio/spl acute/, Universitat Polite/spl acute/cnica de Catalunya, Barcelona, Spain. The system noise temperature was excellent, mainly due to the very low noise performance of the FEM amplifiers, which achieved an average noise temperature of 9.4 K.Peer Reviewe
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